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MC14520BFEL

更新时间： 2024-09-09 04:59:27
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 113K
描述
Dual Up Counters

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中文翻译

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MC14520BFEL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.13
计数方向：UP系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：10.2 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
湿度敏感等级：3位数：4
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED传播延迟（tpd）：560 ns
认证状态：Not Qualified座面最大高度：2.05 mm
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.275 mm最小 fmax：4 MHz
Base Number Matches：1

MC14520BFEL 数据手册

 浏览型号MC14520BFEL的Datasheet PDF文件第2页浏览型号MC14520BFEL的Datasheet PDF文件第3页浏览型号MC14520BFEL的Datasheet PDF文件第4页浏览型号MC14520BFEL的Datasheet PDF文件第5页浏览型号MC14520BFEL的Datasheet PDF文件第6页浏览型号MC14520BFEL的Datasheet PDF文件第7页 
MC14518B, MC14520B  
Dual Up Counters  
The MC14518B dual BCD counter and the MC14520B dual binary  
counter are constructed with MOS P−channel and N−channel  
enhancement mode devices in a single monolithic structure. Each  
consists of two identical, independent, internally synchronous 4−stage  
counters. The counter stages are type D flip−flops, with interchangeable  
Clock and Enable lines for incrementing on either the positive−going or  
negative−going transition as required when cascading multiple stages.  
Each counter can be cleared by applying a high level on the Reset line.  
In addition, the MC14518B will count out of all undefined states within  
two clock periods. These complementary MOS up counters find  
primary use in multi−stage synchronous or ripple counting applications  
requiring low power dissipation and/or high noise immunity.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
P SUFFIX  
CASE 648  
MC145xxBCP  
AWLYYWWG  
Features  
1
• Diode Protection on All Inputs  
16  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Internally Synchronous for High Internal and External Speeds  
SOIC−16  
DW SUFFIX  
CASE 751G  
145xxB  
AWLYYWWG  
• Logic Edge−Clocked Design — Incremented on Positive Transition  
of Clock or Negative Transition on Enable  
• Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
• Pb−Free Packages are Available*  
1
16  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC145xxB  
ALYWG  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
1
V
DD  
DC Supply Voltage Range  
−0.5 to +18.0  
xx  
= 18 or 20  
V , V  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
in out  
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
WW, W = Work Week  
G
= Pb−Free Indicator  
P
D
Power Dissipation,  
500  
mW  
per Package (Note 2.)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
T
Operating Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
T
Lead Temperature  
L
(8−Second Soldering)  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Maximum Ratings are those values beyond which damage to the device  
may occur.  
2. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 5  
MC14518B/D  
 
1234567...9

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