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MC145220DTR2 PDF预览

MC145220DTR2

更新时间： 2024-11-04 14:53:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理光电二极管
页数 文件大小 规格书
25页 208K
描述
PLL Frequency Synthesizer, BICMOS, PDSO20, TSSOP-20

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MC145220DTR2 数据手册

 浏览型号MC145220DTR2的Datasheet PDF文件第2页浏览型号MC145220DTR2的Datasheet PDF文件第3页浏览型号MC145220DTR2的Datasheet PDF文件第4页浏览型号MC145220DTR2的Datasheet PDF文件第5页浏览型号MC145220DTR2的Datasheet PDF文件第6页浏览型号MC145220DTR2的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
F SUFFIX  
SOG PACKAGE  
CASE 803C  
BiCMOS  
20  
1
The MC145220 is a low–voltage, single–chip frequency synthesizer with  
serial interface capable of direct usage up to 1.1 GHz. The device simulta-  
neously supports two loops. The two on–chip dual–modulus prescalers may be  
independently programmed to divide by either 32/33 or 64/65.  
DT SUFFIX  
TSSOP  
CASE 948D  
20  
1
The device consists of two dual–modulus prescalers, two 6–stage A  
counters, two 12–stage N counters, two fully programmable 13–stage R  
(reference) counters, and two lock detectors. Four phase/frequency detectors  
are included: two with current source/sink outputs and two with double–ended  
outputs.  
ORDERING INFORMATION  
MC145220F  
SOG Package  
MC145220DT TSSOP  
The counters are programmed via a synchronous serial port which is SPI  
compatible. The serial port is byte–oriented to facilitate control via an MCU. Due  
to the innovative BitGrabber Plus registers, the MC145220 may be cascaded  
with other peripherals featuring BitGrabber Plus without requiring leading  
dummy bits or multiple address bits in the serial data stream. In addition,  
BitGrabber Plus peripherals may be cascaded with existing BitGrabber  
peripherals. Because this device is a dual synthesizer, a single steering bit is  
used in the serial data stream to direct the data to either side of the chip.  
The phase/frequency detectors have linear transfer functions (no dead  
zones). The current delivered by the current source/sink outputs is controllable  
via the serial port.  
PIN ASSIGNMENT  
REF  
in  
1
2
3
4
5
6
20  
19  
D
in  
CLK  
REF  
out  
LD  
18 LD′  
PD /φ  
out  
17 PD ′/φ ′  
R
R
out  
Rx′/φ ′  
16  
15 GND′  
Rx/φ  
V
V
GND  
Also featured are low–power standby for either one or both loops and  
on–board support of an external crystal. In addition, the part may be configured  
f ′  
f
7
8
14  
13  
in  
in  
f
in  
f ′  
in  
such that the REF pin accepts an external reference signal. In this  
in  
configuration, the REF  
pin may be programmed to output the REF  
in  
out  
frequency divided by 1, 2, 4, 8, or 16.  
V+′  
V+  
9
12  
OUTPUT A 10  
11 ENB  
•
•
•
Operating Frequency: 40 to 1100 MHz  
Operating Supply Voltage Range: 2.7 to 5.5 V  
Supply Current: Both PLLs Operating — 12 mA Nominal  
One PLL Operating, One on Standby — 6.5 mA Nominal  
Both PLLs on Standby — 30 µA Maximum  
Phase Detector Output Current: Up to 2 mA @ 5 V  
Up to 1 mA @ 3 V  
•
•
•
•
Operating Temperature Range: – 40 to 85°C  
Independent R Counters Allow Use of Different Step Sizes for Each Loop  
Double–Buffered R Register — Reference and Loop Divide Ratios  
Updated Simultaneously  
•
•
R Counter Division Range: 1 and 10 to 8,191  
Dual–Modulus Capability Provides Total Division of the VCO Frequency up  
to 262,143  
•
•
•
Direct Interface to Motorola SPI Data Port  
Evaluation Kit Available (Part Number MC145220EVK)  
See Application Note AN1253/D for Low–Pass Filter Design, and  
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping  
REV 4  
1/98  
TN98012300  
MC145220  
4.2–168  
MOTOROLA WIRELESS RF, IF AND TRANSMITTER DEVICE DATA  
1234567...25

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