MC14526B
Presettable 4−Bit Down
Counters
The MC14526B binary counter is constructed with MOS P−channel
and N−channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
http://onsemi.com
MARKING
DIAGRAMS
This complementary MOS counter can be used in frequency
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
MC14526BCP
AWLYYWWG
1
1
PDIP−16
P SUFFIX
CASE 648
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge−Clocked Design: Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
14526B
AWLYWWG
• Asynchronous Preset Enable
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pb−Free Packages are Available*
1
SOIC−16 WB
DW SUFFIX
CASE 751G
1
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
MC14526B
ALYWG
DC Supply Voltage Range
V
−0.5 to +18.0
DD
Input or Output Voltage Range
(DC or Transient)
V ,
−0.5 to V + 0.5
V
in
DD
1
SOEIAJ−16
F SUFFIX
CASE 966
1
V
out
Input or Output Current
(DC or Transient) per Pin
I , I
in out
10
mA
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
P
T
500
mW
°C
D
−55 to +125
−65 to +150
260
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
A
T
stg
°C
Lead Temperature
(8−Second Soldering)
T
°C
WW, W = Work Week
= Pb−Free Package
L
G
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 5
MC14526B/D