SEMICONDUCTOR TECHNICAL DATA
The MC14527B BCD rate multiplier (DRM) provides an output pulse rate
based upon the BCD input number. For example, if 6 is the BCD input
number, there will be six output pulses for every ten input pulses. This part
may be used for arithmetic operations including multiplication and division.
Typical applications include digital filters, motor speed control and frequency
synthesizers.
L SUFFIX
CERAMIC
CASE 620
•
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Output Clocked on the Negative Going Edge of Clock
Strobe for Inhibiting or Enabling Outputs
Enable and Cascade Inputs for Cascade Operation of Two or More
DRMs
“9” Output for the Parallel Enable Configuration and DRMs in Cascade
Complementary Outputs
Clear and Set to Nine Inputs
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
•
•
•
ORDERING INFORMATION
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
T
A
= – 55° to 125°C for all packages.
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
BLOCK DIAGRAM
T
stg
– 65 to + 150
260
4
T
Lead Temperature (8–Second Soldering)
C
L
S
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
12
7
6
5
E
CASC
out
E
11
9
in
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
RATE INPUT
MULTIPLIER
CLOCK
OUT
OUT
“9”
10
14
ST
A
TRUTH TABLE (X = Don’t Care, *D = Most Significant Bit)
Output
B
15
2
Logic Level
C
Number of Pulses
Inputs
3
No. of
Clock
Pulses
D
1
CLEAR
D*
C
B
A
E
Strobe
Cascade Clear
Set
Out
Out
E
“9”
in
out
1
13
0
0
0
0
0
0
0
1
10
10
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
V
= PIN 16
V = PIN 8
SS
0
1
DD
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
4
5
6
2
3
4
5
6
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
8
9
7
8
9
8
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X
10
10
10
10
10
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
9
8
9
1
1
1
1
1
1
8
8
1
9
9
1
—
—
—
—
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10
10
10
10
10
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
1
0
1
1
1
1
0
1
1
0
0
1
10
0
10
1
0
X
0
1
REV 3
1/94
Motorola, Inc. 1995
MOTOROLA CMOS LOGIC DATA
MC14527B
1