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MC14526BCL PDF预览

MC14526BCL

更新时间: 2024-11-04 04:59:27
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摩托罗拉 - MOTOROLA 计数器
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10页 277K
描述
Presettable 4-Bit Down Counters

MC14526BCL 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14522B BCD counter and the MC14526B binary counter are  
constructed with MOS P–channel and N–channel enhancement mode  
devices in a monolithic structure.  
L SUFFIX  
CERAMIC  
CASE 620  
These devices are presettable, cascadable, synchronous down counters  
with a decoded “0” state output for divide–by–N applications. In single stage  
applications the “0” output is applied to the Preset Enable input. The  
Cascade Feedback input allows cascade divide–by–N operation with no  
additional gates required. The Inhibit input allows disabling of the pulse  
counting function. Inhibit may also be used as a negative edge clock.  
These complementary MOS counters can be used in frequency synthesiz-  
ers, phase–locked loops, and other frequency division applications requiring  
low power dissipation and/or high noise immunity.  
P SUFFIX  
PLASTIC  
CASE 648  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Logic Edge–Clocked Design — Incremented on Positive Transition of  
Clock or Negative Transition of Inhibit  
Asynchronous Preset Enable  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
DW SUFFIX  
SOIC  
CASE 751G  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBDW  
Plastic  
Ceramic  
SOIC  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
T
A
= – 55° to 125°C for all packages.  
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
PIN ASSIGNMENT  
Q3  
P3  
PE  
1
2
16  
15  
V
DD  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
Q2  
T
stg  
– 65 to + 150  
260  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
P2  
T
Lead Temperature (8–Second Soldering)  
C
L
INHIBIT  
P0  
CF  
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
“0”  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
CLOCK  
Q0  
P1  
RESET  
Q1  
FUNCTION TABLE  
Inputs  
Output  
V
SS  
Resulting  
Function  
Preset Cascade  
Enable Feedback  
Clock Reset Inhibit  
“0”  
X
X
X
H
H
H
X
X
X
L
H
X
L
L
H
L
H
H
Asynchronous reset*  
Asynchronous reset  
Asynchronous reset  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
X
L
X
H
H
X
L
Asynchronous preset  
L
L
L
L
X
X
L
L
Decrement inhibited  
Decrement inhibited  
L
operation, V and V  
should be constrained  
in  
out  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
No change** (inactive edge)  
No change** (inactive edge)  
Decrement**  
to the range V  
(V or V  
in out  
)
V
DD  
.
SS  
H
H
Unused inputs must always be tied to an  
appropriatelogic voltage level (e.g., either V  
SS  
Decrement**  
or V ). Unused outputs must be left open.  
DD  
X = Don’t Care  
NOTES:  
*Output “0” is low when reset goes high only it PE and CF are low.  
**Output “0” is high when reset is low, only if CF is high and count is 0000.  
REV 3  
1/94  
Motorola, Inc. 1995  

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