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MC14526BDWG PDF预览

MC14526BDWG

更新时间: 2024-09-29 12:34:19
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 156K
描述
Presettable 4-Bit Down Counters

MC14526BDWG 技术参数

是否无铅:不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP16,.4
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:2 weeks
风险等级:0.92Is Samacsys:N
计数方向:DOWN系列:4000/14000/40000
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.3 mm负载电容(CL):50 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:1500000 Hz最大I(ol):0.00064 A
工作模式:SYNCHRONOUS湿度敏感等级:3
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5/15 V
传播延迟(tpd):1100 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Counters
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:7.5 mm最小 fmax:4 MHz
Base Number Matches:1

MC14526BDWG 数据手册

 浏览型号MC14526BDWG的Datasheet PDF文件第2页浏览型号MC14526BDWG的Datasheet PDF文件第3页浏览型号MC14526BDWG的Datasheet PDF文件第4页浏览型号MC14526BDWG的Datasheet PDF文件第5页浏览型号MC14526BDWG的Datasheet PDF文件第6页浏览型号MC14526BDWG的Datasheet PDF文件第7页 
MC14526B  
Presettable 4-Bit Down  
Counters  
The MC14526B binary counter is constructed with MOS Pchannel  
and Nchannel enhancement mode devices in a monolithic structure.  
This device is presettable, cascadable, synchronous down counter  
with a decoded “0” state output for dividebyN applications. In  
single stage applications the “0” output is applied to the Preset Enable  
input. The Cascade Feedback input allows cascade dividebyN  
operation with no additional gates required. The Inhibit input allows  
disabling of the pulse counting function. Inhibit may also be used as a  
negative edge clock.  
http://onsemi.com  
MARKING  
DIAGRAMS  
This complementary MOS counter can be used in frequency  
synthesizers, phaselocked loops, and other frequency division  
applications requiring low power dissipation and/or high noise  
immunity.  
MC14526BCP  
AWLYYWWG  
1
1
PDIP16  
P SUFFIX  
CASE 648  
Features  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Logic EdgeClocked Design: Incremented on Positive Transition of  
Clock or Negative Transition of Inhibit  
Asynchronous Preset Enable  
14526B  
AWLYWWG  
Capable of Driving Two LowPower TTL Loads or One LowPower  
Schottky TTL Load Over the Rated Temperature Range  
These Devices are PbFree and are RoHS Compliant  
1
SOIC16 WB  
DW SUFFIX  
CASE 751G  
1
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
= PbFree Package  
MAXIMUM RATINGS  
G
Rating  
Symbol  
Value  
Unit  
V
DC Supply Voltage Range  
V
DD  
0.5 to +18.0  
Input or Output Voltage Range  
(DC or Transient)  
V ,  
out  
0.5 to V + 0.5  
V
in  
DD  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
V
Input or Output Current  
(DC or Transient) per Pin  
I , I  
in out  
10  
mA  
Power Dissipation per Package (Note 1)  
Operating Temperature Range  
Storage Temperature Range  
P
500  
mW  
°C  
D
T
A
55 to +125  
65 to +150  
260  
T
stg  
°C  
Lead Temperature  
(8Second Soldering)  
T
°C  
L
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
highimpedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
May, 2013 Rev. 7  
MC14526B/D  
 

MC14526BDWG 替代型号

型号 品牌 替代类型 描述 数据表
MC14526BFG ONSEMI

完全替代

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MC14526BDWR2G ONSEMI

完全替代

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完全替代

Presettable 4-Bit Down Counters

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