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MC14526BDW

更新时间： 2024-09-29 04:59:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 277K
描述
Presettable 4-Bit Down Counters

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MC14526BDW 技术参数

生命周期：Transferred零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.52Is Samacsys：N
计数方向：DOWN系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16JESD-609代码：e0
长度：10.3 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：1500000 Hz最大I（ol）：0.00064 A
工作模式：SYNCHRONOUS位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5/15 V
传播延迟（tpd）：1100 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Counters
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.5 mm
最小 fmax：4 MHzBase Number Matches：1

MC14526BDW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14522B BCD counter and the MC14526B binary counter are  
constructed with MOS P–channel and N–channel enhancement mode  
devices in a monolithic structure.  
L SUFFIX  
CERAMIC  
CASE 620  
These devices are presettable, cascadable, synchronous down counters  
with a decoded “0” state output for divide–by–N applications. In single stage  
applications the “0” output is applied to the Preset Enable input. The  
Cascade Feedback input allows cascade divide–by–N operation with no  
additional gates required. The Inhibit input allows disabling of the pulse  
counting function. Inhibit may also be used as a negative edge clock.  
These complementary MOS counters can be used in frequency synthesiz-  
ers, phase–locked loops, and other frequency division applications requiring  
low power dissipation and/or high noise immunity.  
P SUFFIX  
PLASTIC  
CASE 648  
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Logic Edge–Clocked Design — Incremented on Positive Transition of  
Clock or Negative Transition of Inhibit  
Asynchronous Preset Enable  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
DW SUFFIX  
SOIC  
CASE 751G  
•
•
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBDW  
Plastic  
Ceramic  
SOIC  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
T
A
= – 55° to 125°C for all packages.  
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
PIN ASSIGNMENT  
Q3  
P3  
PE  
1
2
16  
15  
V
DD  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
Q2  
T
stg  
– 65 to + 150  
260  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
P2  
T
Lead Temperature (8–Second Soldering)  
C
L
INHIBIT  
P0  
CF  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
“0”  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
CLOCK  
Q0  
P1  
RESET  
Q1  
FUNCTION TABLE  
Inputs  
Output  
V
SS  
Resulting  
Function  
Preset Cascade  
Enable Feedback  
Clock Reset Inhibit  
“0”  
X
X
X
H
H
H
X
X
X
L
H
X
L
L
H
L
H
H
Asynchronous reset*  
Asynchronous reset  
Asynchronous reset  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
X
L
X
H
H
X
L
Asynchronous preset  
L
L
L
L
X
X
L
L
Decrement inhibited  
Decrement inhibited  
L
operation, V and V  
should be constrained  
in  
out  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
No change** (inactive edge)  
No change** (inactive edge)  
Decrement**  
to the range V  
(V or V  
in out  
)
V
DD  
.
SS  
H
H
Unused inputs must always be tied to an  
appropriatelogic voltage level (e.g., either V  
SS  
Decrement**  
or V ). Unused outputs must be left open.  
DD  
X = Don’t Care  
NOTES:  
*Output “0” is low when reset goes high only it PE and CF are low.  
**Output “0” is high when reset is low, only if CF is high and count is 0000.  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567...10

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