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MC14520BALD PDF预览

MC14520BALD

更新时间： 2024-11-18 12:58:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
7页 206K
描述
4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16

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MC14520BALD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.16
计数方向：UP系列：4000/14000/40000
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：19.3 mm负载电容（CL）：50 pF
负载/预设输入：NO逻辑集成电路类型：BINARY COUNTER
工作模式：SYNCHRONOUS位数：4
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：560 ns
认证状态：Not Qualified座面最大高度：4.19 mm
子类别：Counters最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：1.5 MHzBase Number Matches：1

MC14520BALD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14518B dual BCD counter and the MC14520B dual binary counter  
are constructed with MOS P–channel and N–channel enhancement mode  
devices in a single monolithic structure. Each consists of two identical,  
independent, internally synchronous 4–stage counters. The counter stages  
are type D flip–flops, with interchangeable Clock and Enable lines for  
incrementing on either the positive–going or negative–going transition as  
required when cascading multiple stages. Each counter can be cleared by  
applying a high level on the Reset line. In addition, the MC14518B will count  
out of all undefined states within two clock periods. These complementary  
MOS up counters find primary use in multi–stage synchronous or ripple  
counting applications requiring low power dissipation and/or high noise  
immunity.  
L SUFFIX  
CERAMIC  
CASE 620  
P SUFFIX  
PLASTIC  
CASE 648  
DW SUFFIX  
SOIC  
CASE 751G  
•
•
•
•
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Internally Synchronous for High Internal and External Speeds  
Logic Edge–Clocked Design — Incremented on Positive Transition of  
Clock or Negative Transition on Enable  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBDW  
Plastic  
Ceramic  
SOIC  
•
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
BLOCK DIAGRAM  
V
I
, V  
Input or Output Voltage (DC or Transient)  
0.5 to V  
DD  
+ 0.5  
V
in out  
CLOCK  
1
, I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
Q0  
3
4
5
6
Q1  
C
2
Q2  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
ENABLE  
Q3  
R
T
stg  
– 65 to + 150  
260  
T
L
Lead Temperature (8–Second Soldering)  
C
7
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
CLOCK  
9
11  
12  
13  
14  
Q0  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
Q1  
C
10  
Q2  
ENABLE  
Q3  
R
TRUTH TABLE  
Clock Enable Reset  
Action  
Increment Counter  
Increment Counter  
No Change  
15  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
1
X
0
0
0
0
0
0
0
1
0
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
operation, V and V  
to the range V  
Unused inputs must always be tied to an  
appropriatelogic voltage level (e.g., either V  
or V ). Unused outputs must be left open.  
DD  
X
No Change  
No Change  
1
No Change  
X
X
Q0 thru Q3 = 0  
should be constrained  
in  
out  
(V or V  
X = Don’t Care  
)
V
DD  
.
SS  
in out  
SS  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567

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