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MC145202D PDF预览

MC145202D

更新时间: 2024-01-12 10:15:44
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摩托罗拉 - MOTOROLA 预分频器
页数 文件大小 规格书
24页 346K
描述
Low-Voltage 2.0 GHz PLL Frequency Synthesizer Includes On-Board 64/65 Prescaler

MC145202D 数据手册

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Order this document  
by MC145202/D  
SEMICONDUCTOR TECHNICAL DATA  
F SUFFIX  
SOG PACKAGE  
CASE 751J  
Includes On–Board 64/65 Prescaler  
20  
The MC145202 is a low–voltage single–package synthesizer with serial  
interface capable of direct usage up to 2.0 GHz.  
1
The counters are programmed via a synchronous serial port which is SPI  
compatible. The serial port is byte-oriented to facilitate control via an MCU. Due  
to the innovative BitGrabber Plus registers, the MC145202 may be cascaded  
with other peripherals featuring BitGrabber Plus without requiring leading  
dummy bits or address bits in the serial data stream. In addition, BitGrabber  
Plus peripherals may be cascaded with existing BitGrabber peripherals.  
The device features a single–ended current source/sink phase detector A  
output and a double–ended phase detector B output. Both phase detectors  
have linear transfer functions (no dead zones). The maximum current of the  
single–ended phase detector output is determined by an external resistor tied  
from the Rx pin to ground. This current can be varied via the serial port.  
DT SUFFIX  
TSSOP  
CASE 948D  
20  
1
ORDERING INFORMATION  
MC145202F  
SOG Package  
MC145202DT TSSOP  
PIN ASSIGNMENT  
Slew–rate control is provided by a special driver designed for the REF  
pin.  
out  
This minimizes interference caused by REF  
.
REF  
1
2
3
4
5
6
20  
19  
18  
17  
16  
15  
REF  
in  
out  
out  
LD  
This part includes a differential RF input that may be operated in a  
single–ended mode. Also featured are on–board support of an external crystal  
and a programmable reference output. The R, A, and N counters are fully  
programmable. The C register (configuration register) allows the part to be  
configured to meet various applications. A patented feature allows the C  
register to shut off unused outputs, thereby minimizing system noise and  
interference.  
D
in  
CLK  
φ
R
φ
V
ENB  
OUTPUT A  
OUTPUT B  
V
PD  
PD  
out  
In order to have consistent lock times and prevent erroneous data from being  
loaded into the counters, on–board circuitry synchronizes the update of the A  
register if the A or N counters are loading. Similarly, an update of the R register  
is synchronized if the R counter is loading.  
The double–buffered R register allows new divide ratios to be presented to  
the three counters (R, A, and N) simultaneously.  
GND  
Rx  
V
7
14  
13  
12  
11  
DD  
8
TEST 2  
TEST 1  
9
V
f
CC  
10  
f
in  
in  
Maximum Operating Frequency: 2000 MHz @ – 10 dBm  
Operating Supply Current: 4 mA Nominal at 3.0 V  
Operating Supply Voltage Range (V  
and V  
Pins): 2.7 to 5.5 V  
DD  
Operating Supply Voltage Range of Phase Detectors (V  
CC  
Pin): 2.7 to 5.5 V  
PD  
Current Source/Sink Phase Detector Output Capability: 1.7 mA @ 5.0 V  
1.0 mA @ 3.0 V  
Gain of Current Source/Sink Phase/Frequency Detector Controllable via  
Serial Port  
Operating Temperature Range: – 40 to + 85°C  
R Counter Division Range: 1 and 5 to 8191  
Dual–Modulus Capability Provides Total Division up to 262,143  
High–Speed Serial Interface: 4 Mbps  
OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices  
Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)  
with Four Output Modes  
OUTPUT B: Open–Drain  
Patented Power–Saving Standby Feature with Orderly Recovery for  
Minimizing Lock Times, Standby Current: 30 µA  
Evaluation Kit Available (Part Number MC145202EVK)  
See Application Note AN1253/D for Low–Pass Filter Design, and  
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping  
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.  
REV 3  
1/98  
TN98012300  
Motorola, Inc. 1998  

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