Datasheet > MC10E193

MC10E193

更新时间： 2024-02-13 23:57:26

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	112K
描述
ERROR DETECTION/ CORRECTION CIRCUIT

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MC10E193 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E193 is an error detection and correction (EDAC)

circuit. Modified Hamming parity codes are generated on an 8-bit word

according to the pattern shown in the logic symbol. The P5 output gives

the parity of the whole word. The word parity is also provided at the PGEN

pin, after Odd/Even parity control and gating with the BPAR input. This

output also feeds to a 1-bit shiftable register, for use as part of a scan ring.

ERROR DETECTION/

CORRECTION CIRCUIT

Used in conjunction with 12-bit parity generators such as the E160, a

SECDED (single error correction, double error detection) error system

can be designed for a multiple of an 8-bit word.

• Hamming Code Generation

• 8-Bit Word, Expandable

• Provides Parity of Whole Word

• Scannable Parity Register

• Extended 100E V

• 75kΩ Input Pulldown Resistors

Range of – 4.2V to – 5.46V

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

B INPUTS

0 3 6 5 7 4 2 1

LOGIC DIAGRAM

B , B , B , B

Pinout: 28-Lead PLCC (Top View)

B , B , B , B

EN HOLD S-IN SHIFT CLK

PGEN

CCO

PARERR

EV/OD

BPAR

B , B , B , B

BYTE (B – B )

CCO

PGEN

BPAR

EV/OD

PARERR

CCO

* All V

and V pins are tied together on the die.

CCO

HOLD

S-IN

SHIFT

CLK

7/96

REV 3

2–1

Motorola, Inc. 1996

12 3 4

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