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MC10E196FNG PDF预览

MC10E196FNG

更新时间: 2024-01-07 14:20:29
品牌 Logo 应用领域
安森美 - ONSEMI 延迟线逻辑集成电路
页数 文件大小 规格书
12页 158K
描述
5V ECL Programmable Delay Chip

MC10E196FNG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.49
Is Samacsys:N其他特性:NECL MODE: VCC=0 WITH VEE=-4.2 V TO -5.7 V
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.505 mm
逻辑集成电路类型:ACTIVE DELAY LINE功能数量:1
抽头/阶步数:127端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
电源:-5.2 V最大电源电流(ICC):156 mA
可编程延迟线:YESProp。Delay @ Nom-Sup:4.72 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Delay Lines最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
总延迟标称(td):3.63 ns宽度:11.505 mm
Base Number Matches:1

MC10E196FNG 数据手册

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MC10E196, MC100E196  
5VꢀECL Programmable  
Delay Chip  
Description  
The MC10E/100E196 is a programmable delay chip (PDC)  
designed primarily for very accurate differential ECL input edge  
placement applications.  
http://onsemi.com  
The delay section consists of a chain of gates and a linear ramp delay  
adjust organized as shown in the logic symbol. The first two delay  
elements feature gates that have been modified to have delays  
1.25 and 1.5 times the basic gate delay of approximately 80 ps. These  
two elements provide the E196 with a digitally-selectable resolution  
of approximately 20 ps. The required device delay is selected by the  
seven address inputs D[0:6], which are latched on chip by a high signal  
on the latch enable (LEN) control.  
PLCC28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1
The FTUNE input takes an analog voltage and applies it to an  
internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)  
minimum resolution still further. The FTUNE input is what  
differentiates the E196 from the E195.  
MCxxxE196FNG  
AWLYYWW  
An eighth latched input, D7, is provided for cascading multiple  
PDC’s for increased programmable range. The cascade logic allows  
full control of multiple PDC’s, at the expense of only a single added  
line to the data bus for each additional PDC, without the need for any  
external gating.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
Features  
2.0 ns Worst Case Delay Range  
20 ps/Delay Step Resolution  
Linear Input for Tighter Resolution  
>1.0 GHz Bandwidth  
On Chip Cascade Circuitry  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
Moisture Sensitivity Level: Pb = 1; PbFree = 3  
For Additional Information, see Application Note  
AND8003/D  
Flammability Rating: UL 94 V0 @ 1.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 425 devices  
PbFree Packages are Available*  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 4.2 V to 5.7 V  
EE  
Internal Input 50 kW Pulldown Resistors  
ESD Protection: Human Body Model; > 1 kV,  
Machine Model; > 75 V  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 9  
MC10E196/D  

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