Datasheet > MC10E196_06

MC10E196_06

更新时间： 2024-02-07 02:09:45

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
12页	158K
描述
5V ECL Programmable Delay Chip

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MC10E196_06 数据手册

MC10E196, MC100E196

5VꢀECL Programmable

Delay Chip

Description

The MC10E/100E196 is a programmable delay chip (PDC)

designed primarily for very accurate differential ECL input edge

placement applications.

http://onsemi.com

The delay section consists of a chain of gates and a linear ramp delay

adjust organized as shown in the logic symbol. The first two delay

elements feature gates that have been modified to have delays

1.25 and 1.5 times the basic gate delay of approximately 80 ps. These

two elements provide the E196 with a digitally-selectable resolution

of approximately 20 ps. The required device delay is selected by the

seven address inputs D[0:6], which are latched on chip by a high signal

on the latch enable (LEN) control.

PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

The FTUNE input takes an analog voltage and applies it to an

internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)

minimum resolution still further. The FTUNE input is what

differentiates the E196 from the E195.

MCxxxE196FNG

AWLYYWW

An eighth latched input, D7, is provided for cascading multiple

PDC’s for increased programmable range. The cascade logic allows

full control of multiple PDC’s, at the expense of only a single added

line to the data bus for each additional PDC, without the need for any

external gating.

xxx

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

*For additional marking information, refer to

Application Note AND8002/D.

to 0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

Features

• 2.0 ns Worst Case Delay Range

• ≈20 ps/Delay Step Resolution

• Linear Input for Tighter Resolution

• >1.0 GHz Bandwidth

• On Chip Cascade Circuitry

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3

For Additional Information, see Application Note

AND8003/D

• Flammability Rating: UL 94 V−0 @ 1.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 425 devices

• Pb−Free Packages are Available*

• PECL Mode Operating Range: V = 4.2 V to 5.7 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

with V = −4.2 V to −5.7 V

• Internal Input 50 kW Pulldown Resistors

• ESD Protection: Human Body Model; > 1 kV,

Machine Model; > 75 V

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 9

MC10E196/D

12 3 4 5 6 7...12

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与MC10E196_06相关器件

型号	品牌	获取价格	描述	数据表
MC10E196FN	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FN	MOTOROLA	获取价格	PROGRAMMABLE DELAY CHIP
MC10E196FNG	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FNR2	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FNR2	MOTOROLA	获取价格	Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28, PLAST
MC10E196FNR2G	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E197	ONSEMI	获取价格	DATA SEPARATOR
MC10E197_06	ONSEMI	获取价格	5V ECL Data Separator
MC10E197FN	ONSEMI	获取价格	5V ECL Data Separator
MC10E197FN	MOTOROLA	获取价格	DATA SEPARATOR

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