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MC10E211FN PDF预览

MC10E211FN

更新时间: 2024-02-22 20:42:41
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟驱动器逻辑集成电路输出元件
页数 文件大小 规格书
7页 105K
描述
1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP

MC10E211FN 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.84
其他特性:SYNCHRONOUS STROBED OUTPUT; WITH DIFFERENTIAL OUTPUT; MAX PART TO PART SKEW = 0.37NS系列:10E
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:28
实输出次数:6最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:-5.2 V
最大电源电流(ICC):142 mAProp。Delay @ Nom-Sup:123 ns
传播延迟(tpd):1.145 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:4.57 mm
子类别:Clock Drivers表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.505 mmBase Number Matches:1

MC10E211FN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E211 is a low skew 1:6 fanout device designed  
explicitly for low skew clock distribution applications. The device can be  
driven by either a differential or single-ended ECL or, if positive power  
supplies are used, PECL input signal (PECL is an acronym for Positive  
ECL, PECL levels are ECL levels referenced to +5V rather than ground).  
If a single-ended input is to be used the V  
pin should be connected to  
the CLK input and bypassed to ground via a 0.01µF capacitor. The V  
1:6 DIFFERENTIAL  
CLOCK DISTRIBUTION CHIP  
BB  
BB  
supply is designed to act as the switching reference for the input of the  
E211 under single-ended input conditions, as a result this pin can only  
source/sink up to 0.5mA of current.  
Guaranteed Low Skew Specification  
Synchronous Enabling/Disabling  
Multiplexed Clock Inputs  
V  
Output for Single-Ended Use  
BB  
Internal 75kInput Pulldown Resistors  
Common and Individual Enable/Disable Control  
High Bandwidth Output Transistors  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
Extended 100E V  
Range of –4.2V to –5.46V  
EE  
The E211 features a multiplexed clock input to allow for the distribution  
of a lower speed scan or test clock along with the high speed system  
clock. When LOW (or left open in which case it will be pulled LOW by the  
input pulldown resistor) the SEL pin will select the differential clock input.  
Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next  
negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be  
enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the  
disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all  
associated specifications are referenced to the negative edge of the CLK input.  
The output transitions of the E211 are faster than the standard ECLinPS edge rates. This feature provides a means of  
distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits  
guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the  
recommended termination schemes please refer to the applications information section of this data sheet.  
FUNCTION TABLE  
CLK  
SCLK  
SEL  
ENx  
Q
H/L  
X
Z*  
X
H/L  
Z*  
L
H
X
L
L
H
CLK  
SCLK  
L
* Z = Negative transition of CLK or SCLK  
ECLinPS is a trademark of Motorola Inc.  
5/95  
REV 3  
Motorola, Inc. 1996  

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