MC10E241

更新时间： 2024-10-30 22:58:07

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	111K
描述
8-BIT SCANNABLE REGISTER

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数据手册

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MC10E241 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E241 is an 8-bit shiftable register. Unlike a standard

universal shift register such as the E141, the E241 features internal data

feedback organized so that the SHIFT control overrides the HOLD/LOAD

control. This enables the normal operations of HOLD and LOAD to be

toggled with a single control line without the need for external gating. It

also enables switching to scan mode with the single SHIFT control line.

The eight inputs D – D accept parallel input data, while S-IN accepts

8-BIT SCANNABLE

serial input data when in shift mode. Data is accepted a set-up time

before the positive-going edge of CLK; shifting is also accomplished on

the positive clock edge. A HIGH on the Master Reset pin (MR)

asynchronously resets all the registers to zero.

• SHIFT overrides HOLD/LOAD Control

• 1000ps Max. CLK to Q

• Asynchronous Master Reset

• Pin-Compatible with E141

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

Pinout: 28-Lead PLCC (Top View)

SEL0

CCO

SEL1

CLK

LOGIC DIAGRAM

S-IN

CCO

– Q

CCO

– D

* All V

and V

pins are tied together on the die.

CCO

BITS 1–6

PIN NAMES

Function

– D

Parallel Date Inputs

Serial Data Inputs

SHIFT Control

HOLD/LOAD Control

Clock

S-IN

SEL0

SEL1

CLK

HOLD/LOAD

SHIFT

Master Reset

CLK

– Q

Data Outputs

7/96

REV 3

2–1

Motorola, Inc. 1996

12 3 4

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与MC10E241相关器件

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MC10E241FN	MOTOROLA	获取价格	8-BIT SCANNABLE REGISTER
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MC10E256FNR2	ONSEMI	获取价格	10E SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PQCC28, PLASTIC, LCC-28
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MC10E336FN	MOTOROLA	获取价格	3-BIT REGISTERED BUS TRANSCEIVER
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MC10E336FNR2	MOTOROLA	获取价格	10E SERIES, 3-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC28, PLASTIC, LCC-28