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MC10E336 PDF预览

MC10E336

更新时间： 2024-10-31 12:46:39
品牌 Logo 应用领域
安森美 - ONSEMI 总线收发器
页数 文件大小 规格书
4页 117K
描述
3-BIT REGISTERED BUS TRANSCEIVER

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中文翻译

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MC10E336 数据手册

 浏览型号MC10E336的Datasheet PDF文件第2页浏览型号MC10E336的Datasheet PDF文件第3页浏览型号MC10E336的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10E/MC100E336 contains three bus transceivers with both  
transmit and receive registers. The bus outputs (BUS0–BUS2) are  
specified for driving a 25Ω bus; the receive outputs (Q0 – Q2) are  
specified for 50Ω. The bus outputs feature a normal HIGH level (V  
) and  
OH  
a cutoff LOW level — when LOW, the outputs go to –2.0V and the output  
emitter-follower is “off”, presenting a high impedance to the bus. The bus  
outputs also feature edge slow-down capacitors.  
3-BIT REGISTERED  
BUS TRANSCEIVER  
• 25Ω Cutoff Bus Outputs  
• 50Ω Receiver Outputs  
• Transmit and Receive Registers  
• 1500ps Max. Clock to Bus  
• 1000ps Max. Clock to Q  
• Bus Outputs Feature Internal Edge Slow-Down Capacitors  
• Additional Package Ground Pins  
• Extended 100E V  
EE  
Range of – 4.2V to – 5.46V  
• 75kΩ Input Pulldown Resistors  
The Transmit Enable pins (TEN) control whether current data is held in  
the transmit register, or new data is loaded from the A/B inputs. A LOW on  
both of the Bus Enable inputs (BUSEN), when clocked through the  
register, disables the bus outputs to –2.0V.  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
The receiver section clocks bus data into the receive registers, after  
gating with the Receive Enable (RXEN) input.  
All registers are clocked by a positive transition of CLK1 or CLK2 (or  
both).  
Additional leadframe grounding is provided through the Ground pins (GND) which should be connected to 0V. The GND pins  
are not electrically connected to the chip.  
LOGIC DIAGRAM  
Pinout: 28-Lead PLCC (Top View)  
TEN2 TEN1  
B
A
NC  
V
Q
2
2
2
CCO  
0
1
D Q  
D Q  
D Q  
25  
25  
25  
Ω
CUTOFF  
A
B
BUS0  
0
0
25 24  
23  
22  
21  
20  
19  
BUSEN1  
BUSEN2  
RXEN  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
GND  
D
50  
Ω
Ω
Q
0
Q
BUS2  
0
1
V
CC  
Ω
CUTOFF  
A
B
BUS1  
1
1
V
Q
EE  
1
D
50  
Q
1
Q
CLK1  
CLK2  
2
V
CCO  
0
1
3
BUS1  
GND  
Ω
CUTOFF  
A
B
2
2
BUS2  
A
4
0
D
50  
Ω
Q
2
Q
5
6
7
8
9
10  
11  
TEN1  
TEN2  
B
A
B
V
BUS0 GND  
Q
0
0
1
1
CCO  
RXEN  
* All V  
and V pins are tied together on the die.  
CCO  
CC  
BUSEN1  
BUSEN2  
D
Q
CLK1  
CLK2  
12/93  
Motorola, Inc. 1996  
REV 2  
1234

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