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MC10E336FNR2 PDF预览

MC10E336FNR2

更新时间: 2024-10-31 20:54:31
品牌 Logo 应用领域
安森美 - ONSEMI 输出元件逻辑集成电路
页数 文件大小 规格书
8页 71K
描述
10E SERIES, 3-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC28, PLASTIC, LCC-28

MC10E336FNR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-28针数:28
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.58其他特性:NECL MODE: 0V VCC WITH VEE = -4.2V TO -5.7V
控制类型:INDEPENDENT CONTROL计数方向:UNIDIRECTIONAL
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.5062 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER位数:3
功能数量:1端口数量:2
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER WITH CUT-OFF
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:-5.2 V最大电源电流(ICC):150 mA
Prop。Delay @ Nom-Sup:1 ns传播延迟(tpd):1 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:11.5062 mmBase Number Matches:1

MC10E336FNR2 数据手册

 浏览型号MC10E336FNR2的Datasheet PDF文件第2页浏览型号MC10E336FNR2的Datasheet PDF文件第3页浏览型号MC10E336FNR2的Datasheet PDF文件第4页浏览型号MC10E336FNR2的Datasheet PDF文件第5页浏览型号MC10E336FNR2的Datasheet PDF文件第6页浏览型号MC10E336FNR2的Datasheet PDF文件第7页 
MC10E336, MC100E336  
5VĄECL 3ĆBit Registered  
Bus Transceiver  
The MC10E/MC100E336 contains three bus transceivers with both  
transmit and receive registers. The bus outputs (BUS0–BUS2) are  
specified for driving a 25 bus; the receive outputs (Q0 – Q2) are  
http://onsemi.com  
MARKING  
specified for 50 . The bus outputs feature a normal HIGH level (V  
)
OH  
and a cutoff LOW level — when LOW, the outputs go to –2.0 V and the  
output emitter-follower is “off”, presenting a high impedance to the bus.  
The bus outputs also feature edge slow-down capacitors.  
The Transmit Enable pins (TEN) control whether current data is  
held in the transmit register, or new data is loaded from the A/B inputs.  
A LOW on both of the Bus Enable inputs (BUSEN), when clocked  
through the register, disables the bus outputs to –2.0 V.  
The receiver section clocks bus data into the receive registers, after  
gating with the Receive Enable (RXEN) input.  
DIAGRAMS  
MC10E336FN  
AWLYYWW  
PLCC–28  
FN SUFFIX  
CASE 776  
All registers are clocked by a positive transition of CLK1 or CLK2  
(or both).  
Additional leadframe grounding is provided through the Ground  
pins (GND) which should be connected to 0 V. The GND pins are not  
electrically connected to the chip.  
28 1  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
MC100E336FN  
AWLYYWW  
The 100 Series contains temperature compensation.  
WW = Work Week  
25 Cutoff Bus Outputs  
50 Receiver Outputs  
28 1  
Transmit and Receive Registers  
1500 ps Max. Clock to Bus  
1000 ps Max. Clock to Q  
Bus Outputs Feature Internal Edge Slow-Down Capacitors  
Additional Package Ground Pins  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10E336FN  
PLCC–28  
37 Units/Rail  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
MC10E336FNR2  
MC100E336FN  
PLCC–28  
PLCC–28  
500 Units/Reel  
37 Units/Rail  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
MC100E336FNR2  
PLCC–28  
500 Units/Reel  
with V = –4.2 V to –5.7 V  
EE  
Internal Input Pulldown Resistors  
ESD Protection: > 1 KV HBM, > 75 V MM  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity Level 1  
For Additional Information, see Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
Transistor Count = 430 devices  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
October, 2000 – Rev. 3  
MC10E336/D  

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