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MC10E431_06

更新时间： 2024-11-05 04:59:39
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安森美 - ONSEMI 触发器
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9页 134K
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5V ECL 3-Bit Differential Flip-Flop

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MC10E431_06 数据手册

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MC10E431, MC100E431  
5VꢀECL 3-Bit Differential  
Flip-Flop  
Description  
The MC10E/100E431 is a 3-bit flip-flop with differential clock,  
data input and data output.  
http://onsemi.com  
The asynchronous Set and Reset controls are edge-triggered rather  
than level controlled. This allows the user to rapidly set or reset the  
flip-flop and then continue clocking at the next clock edge, without the  
necessity of de-asserting the set/reset signal (as would be the case with  
a level controlled set/reset).  
PLCC−28  
FN SUFFIX  
CASE 776  
The E431 is also designed with larger internal swings, an approach  
intended to minimize the time spent crossing the threshold region and  
thus reduce the metastability susceptibility window.  
MARKING DIAGRAM*  
The differential input structures are clamped so that the inputs of  
unused registers can be left open without upsetting the bias network of  
the device. The clamping action will assert the D and the CLK sides of  
the inputs. Because of the edge triggered flip-flop nature of the device  
simultaneously opening both the clock and data inputs will result in an  
output which reaches an unidentified but valid state. Note that the  
1 28  
MCxxxE431FNG  
AWLYYWW  
input clamps only operate when both inputs fall to 2.5 V below V  
.
CC  
The V pin, an internally generated voltage supply, is available to  
this device only. For single-ended input conditions, the unused  
BB  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
differential input is connected to V as a switching reference voltage.  
BB  
V
may also rebias AC coupled inputs. When used, decouple V  
BB  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
*For additional marking information, refer to  
Application Note AND8002/D.  
Features  
• Edge-Triggered Asynchronous Set and Reset  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
• Differential D, CLK and Q; V Reference Available  
BB  
• 1100 MHz Min. Toggle Frequency  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
CC  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
• Transistor Count = 348 devices  
• Pb−Free Packages are Available*  
Charged Device Model; > 2 kV  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 10  
MC10E431/D  
1234567...9

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