5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 延迟线> MC10E196FNR2G
MC10E196FNR2G PDF预览

MC10E196FNR2G

更新时间： 2024-02-22 00:40:11
品牌 Logo 应用领域
安森美 - ONSEMI 延迟线
页数 文件大小 规格书
12页 158K
描述
5V ECL Programmable Delay Chip

阅读下载

中文翻译

获取价格

MC10E196FNR2G 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCJ, LDCC28,.5SQ针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：2 weeks 2 days风险等级：5.13
Is Samacsys：NBase Number Matches：1

MC10E196FNR2G 数据手册

 浏览型号MC10E196FNR2G的Datasheet PDF文件第2页浏览型号MC10E196FNR2G的Datasheet PDF文件第3页浏览型号MC10E196FNR2G的Datasheet PDF文件第4页浏览型号MC10E196FNR2G的Datasheet PDF文件第5页浏览型号MC10E196FNR2G的Datasheet PDF文件第6页浏览型号MC10E196FNR2G的Datasheet PDF文件第7页 
MC10E196, MC100E196  
5VꢀECL Programmable  
Delay Chip  
Description  
The MC10E/100E196 is a programmable delay chip (PDC)  
designed primarily for very accurate differential ECL input edge  
placement applications.  
http://onsemi.com  
The delay section consists of a chain of gates and a linear ramp delay  
adjust organized as shown in the logic symbol. The first two delay  
elements feature gates that have been modified to have delays  
1.25 and 1.5 times the basic gate delay of approximately 80 ps. These  
two elements provide the E196 with a digitally-selectable resolution  
of approximately 20 ps. The required device delay is selected by the  
seven address inputs D[0:6], which are latched on chip by a high signal  
on the latch enable (LEN) control.  
PLCC−28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1
The FTUNE input takes an analog voltage and applies it to an  
internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)  
minimum resolution still further. The FTUNE input is what  
differentiates the E196 from the E195.  
MCxxxE196FNG  
AWLYYWW  
An eighth latched input, D7, is provided for cascading multiple  
PDC’s for increased programmable range. The cascade logic allows  
full control of multiple PDC’s, at the expense of only a single added  
line to the data bus for each additional PDC, without the need for any  
external gating.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
Features  
• 2.0 ns Worst Case Delay Range  
• ≈20 ps/Delay Step Resolution  
• Linear Input for Tighter Resolution  
• >1.0 GHz Bandwidth  
• On Chip Cascade Circuitry  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Flammability Rating: UL 94 V−0 @ 1.125 in,  
Oxygen Index: 28 to 34  
• Transistor Count = 425 devices  
• Pb−Free Packages are Available*  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −4.2 V to −5.7 V  
EE  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 1 kV,  
Machine Model; > 75 V  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 9  
MC10E196/D  
1234567...12

中文翻译

下载PDF

MC10E196FNR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP196BMNG ONSEMI

功能相似

 3.3 V ECL Programmable Delay Chip With FTUNE
MC100EP195BFAG ONSEMI

功能相似

 3.3V ECL Programmable Delay Chip
MC100EP195FAG ONSEMI

功能相似

 3.3V ECL Programmable Delay Chip

与MC10E196FNR2G相关器件

型号 品牌 获取价格 描述 数据表
MC10E197 ONSEMI

获取价格

 		DATA SEPARATOR
MC10E197_06 ONSEMI

获取价格

 		5V ECL Data Separator
MC10E197FN ONSEMI

获取价格

 		5V ECL Data Separator
MC10E197FN MOTOROLA

获取价格

 		DATA SEPARATOR
MC10E197FNR2 ONSEMI

获取价格

 		5V ECL Data Separator
MC10E211 ONSEMI

获取价格

 		1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC10E211_06 ONSEMI

获取价格

 		5V ECL 1:6 Differential Clock Distribution Chip
MC10E211FN ONSEMI

获取价格

 		5V ECL 1:6 Differential Clock Distribution Chip
MC10E211FN MOTOROLA

获取价格

 		1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC10E211FNG ONSEMI

获取价格

 		5V ECL 1:6 Differential Clock Distribution Chip

与MC10E196FNR2G相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证