MC10E211

更新时间： 2024-02-14 17:32:30

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
7页	126K
描述
1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP

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MC10E211 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E211 is a low skew 1:6 fanout device designed

explicitly for low skew clock distribution applications. The device can be

driven by either a differential or single-ended ECL or, if positive power

supplies are used, PECL input signal (PECL is an acronym for Positive

ECL, PECL levels are ECL levels referenced to +5V rather than ground).

If a single-ended input is to be used the V

pin should be connected to

the CLK input and bypassed to ground via a 0.01µF capacitor. The V

1:6 DIFFERENTIAL

CLOCK DISTRIBUTION CHIP

supply is designed to act as the switching reference for the input of the

E211 under single-ended input conditions, as a result this pin can only

source/sink up to 0.5mA of current.

• Guaranteed Low Skew Specification

• Synchronous Enabling/Disabling

• Multiplexed Clock Inputs

• V

Output for Single-Ended Use

• Internal 75kΩ Input Pulldown Resistors

• Common and Individual Enable/Disable Control

• High Bandwidth Output Transistors

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

• Extended 100E V

Range of –4.2V to –5.46V

The E211 features a multiplexed clock input to allow for the distribution

of a lower speed scan or test clock along with the high speed system

clock. When LOW (or left open in which case it will be pulled LOW by the

input pulldown resistor) the SEL pin will select the differential clock input.

Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next

negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be

enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the

disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all

associated specifications are referenced to the negative edge of the CLK input.

The output transitions of the E211 are faster than the standard ECLinPS edge rates. This feature provides a means of

distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits

guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the

recommended termination schemes please refer to the applications information section of this data sheet.

FUNCTION TABLE

CLK

SCLK

SEL

ENx

H/L

CLK

SCLK

* Z = Negative transition of CLK or SCLK

ECLinPS is a trademark of Motorola Inc.

5/95

REV 3

2–1

Motorola, Inc. 1996

12 3 4 5 6 7

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与MC10E211相关器件

型号	品牌	获取价格	描述	数据表
MC10E211_06	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC10E211FN	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC10E211FN	MOTOROLA	获取价格	1:6 DIFFERENTIAL CLOCK DISTRIBUTION CHIP
MC10E211FNG	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC10E211FNR2	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC10E211FNR2G	ONSEMI	获取价格	5V ECL 1:6 Differential Clock Distribution Chip
MC10E212	ONSEMI	获取价格	3-BIT SCANNABLE REGISTERED ADDRESS DRIVER
MC10E212_06	ONSEMI	获取价格	5V ECL 3-Bit Scannable Registered Address Driver
MC10E212FN	ONSEMI	获取价格	5V ECL 3-Bit Scannable Registered Address Driver
MC10E212FN	MOTOROLA	获取价格	3-BIT SCANNABLE REGISTERED ADDRESS DRIVER

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