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MC10E211_06

更新时间: 2024-02-11 02:59:59
品牌 Logo 应用领域
安森美 - ONSEMI 时钟
页数 文件大小 规格书
11页 151K
描述
5V ECL 1:6 Differential Clock Distribution Chip

MC10E211_06 数据手册

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MC10E211, MC100E211  
5VꢀECL 1:6 Differential  
Clock Distribution Chip  
Description  
The MC10E/100E211 is a low skew 1:6 fanout device designed  
explicitly for low skew clock distribution applications.  
http://onsemi.com  
The E211 features a multiplexed clock input to allow for the  
distribution of a lower speed scan or test clock along with the high  
speed system clock. When LOW (or left open in which case it will be  
pulled LOW by the input pulldown resistor) the SEL pin will select the  
differential clock input.  
PLCC28  
FN SUFFIX  
CASE 776  
Both a common enable and individual output enables are provided.  
When asserted the positive output will go LOW on the next negative  
transition of the CLK (or SCLK) input. The enabling function is  
synchronous so that the outputs will only be enabled/disabled when  
the outputs are already in the LOW state. In this way the problem of  
runt pulse generation during the disable operation is avoided. Note that  
the internal flip flop is clocked on the falling edge of the input clock  
edge, therefore all associated specifications are referenced to the  
negative edge of the CLK input.  
MARKING DIAGRAM*  
1
MCxxxE211FNG  
AWLYYWW  
The output transitions of the E211 are faster than the standard  
ECLinPS edge rates. This feature provides a means of distributing  
higher frequency signals than capable with the E111 device. Because  
of these edge rates and the tight skew limits guaranteed in the  
specification, there are certain termination guidelines which must be  
followed. For more details on the recommended termination schemes  
please refer to the applications information section of this data sheet.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For singleended input conditions, the unused  
*For additional marking information, refer to  
Application Note AND8002/D.  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
Guaranteed Low Skew Specification  
Synchronous Enabling/Disabling  
Multiplexed Clock Inputs  
ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 100 V  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
Moisture Sensitivity Level: Pb = 1; PbFree = 3  
For Additional Information, see Application Note  
AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
V Output for SingleEnded Use  
BB  
Common and Individual Enable/Disable Control  
High Bandwidth Output Transistors  
PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V with V  
=
CC  
EE  
Transistor Count = 457 devices  
PbFree Packages are Available*  
4.2 V to 5.7 V  
Internal Input 75 kW Pulldown Resistors  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 12  
MC10E211/D  

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