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MC10E195FNR2G PDF预览

MC10E195FNR2G

更新时间： 2024-01-25 17:04:39
品牌 Logo 应用领域
安森美 - ONSEMI 延迟线逻辑集成电路
页数 文件大小 规格书
11页 151K
描述
5V ECL Programmable Delay Chip

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MC10E195FNR2G 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCJ, LDCC28,.5SQ针数：28
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.58
Is Samacsys：N其他特性：NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列：10EJESD-30 代码：S-PQCC-J28
JESD-609代码：e3长度：11.505 mm
逻辑集成电路类型：ACTIVE DELAY LINE湿度敏感等级：3
功能数量：1抽头/阶步数：127
端子数量：28最高工作温度：85 °C
最低工作温度：输出特性：OPEN-EMITTER
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：-5.2 V
最大电源电流（ICC）：156 mA可编程延迟线：YES
Prop。Delay @ Nom-Sup：4.72 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Delay Lines
最大供电电压 (Vsup)：5.7 V最小供电电压 (Vsup)：4.2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：ECL温度等级：OTHER
端子面层：Tin (Sn)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40总延迟标称（td）：3.63 ns
宽度：11.505 mmBase Number Matches：1

MC10E195FNR2G 数据手册

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MC10E195, MC100E195  
5VꢀECL Programmable  
Delay Chip  
Description  
The MC10E/100E195 is a programmable delay chip (PDC)  
designed primarily for clock de-skewing and timing adjustment. It  
provides variable delay of a differential ECL input transition.  
The delay section consists of a chain of gates organized as shown in  
the logic symbol. The first two delay elements feature gates that have  
been modified to have delays 1.25 and 1.5 times the basic gate delay of  
approximately 80 ps. These two elements provide the E195 with a  
digitally-selectable resolution of approximately 20 ps. The required  
device delay is selected by the seven address inputs D[0:6], which are  
latched on chip by a high signal on the latch enable (LEN) control.  
Because the delay programmability of the E195 is achieved by  
purely differential ECL gate delays the device will operate at  
frequencies of > 1.0 GHz while maintaining over 600 mV of output  
swing.  
http://onsemi.com  
PLCC−28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
1
MCxxxE195FNG  
AWLYYWW  
The E195 thus offers very fine resolution, at very high frequencies,  
that is selectable entirely from a digital input allowing for very  
accurate system clock timing.  
An eighth latched input, D7, is provided for cascading multiple  
PDC’s for increased programmable range. The cascade logic allows  
full control of multiple PDC’s, at the expense of only a single added  
line to the data bus for each additional PDC, without the need for any  
external gating.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
*For additional marking information, refer to  
Application Note AND8002/D.  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
to 0.5 mA. When not used, V should be left open.  
BB  
The 100 Series contains temperature compensation.  
Features  
• 2.0 ns Worst Case Delay Range  
• ≈20 ps/Delay Step Resolution  
• >1.0 GHz Bandwidth  
• On Chip Cascade Circuitry  
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC  
Latchup Test  
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3  
For Additional Information, see Application Note  
AND8003/D  
• Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
• Transistor Count = 368 devices  
• PECL Mode Operating Range: V = 4.2 V to 5.7 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −4.2 V to −5.7 V  
EE  
• Pb−Free Packages are Available*  
• Internal Input 50 kW Pulldown Resistors  
• ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 10  
MC10E195/D  
1234567...11

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MC10E195FNR2G 替代型号

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