MC10E196

更新时间： 2024-02-01 12:59:12

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
7页	152K
描述
PROGRAMMABLE DELAY CHIP

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数据手册

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MC10E196 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E196 is a programmable delay chip (PDC) designed

primarily for very accurate differential ECL input edge placement

applications.

The delay section consists of a chain of gates and a linear ramp delay

adjust organized as shown in the logic symbol. The first two delay

elements feature gates that have been modified to have delays 1.25 and

1.5 times the basic gate delay of approximately 80 ps. These two

elements provide the E196 with a digitally-selectable resolution of

approximately 20 ps. The required device delay is selected by the seven

address inputs D[0:6], which are latched on chip by a high signal on the

latch enable (LEN) control.

PROGRAMMABLE

DELAY CHIP

The FTUNE input takes an analog voltage and applies it to an internal

linear ramp for reducing the 20 ps resolution still further. The FTUNE input

is what differentiates the E196 from the E195.

An eighth latched input, D7, is provided for cascading multiple PDC’s

for increased programmable range. The cascade logic allows full control

of multiple PDC’s, at the expense of only a single added line to the data

bus for each additional PDC, without the need for any external gating.

• 2.0ns Worst Case Delay Range

• ≈20ps/Delay Step Resolution

• Linear Input for Tighter Resolution

• >1.0GHz Bandwidth

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

• On Chip Cascade Circuitry

• Extended 100E V

Range of –4.2 to –5.46V

• 75KΩ Input Pulldown Resistors

PIN NAMES

Function

IN/IN

Signal Input

Input Enable

D[0:7]

Q/Q

LEN

Mux Select Inputs

Signal Output

Latch Enable

SET MIN

SET MAX

CASCADE

FTUNE

Min Delay Set

Max Delay Set

Cascade Signal

Linear Voltage Input

LOGIC DIAGRAM – SIMPLIFIED

FTUNE

4 GATES

8 GATES

16 GATES

* 1.25

* 1.5

LINEAR

RAMP

CASCADE

LEN

LATCH

LEN

SET MIN

SET MAX

7 BIT LATCH

CASCADE

* DELAYS ARE 25% OR 50% LONGER THAN

* STANDARD (STANDARD 80 PS)

≈

12/93

Motorola, Inc. 1996

REV 2

2–1

12 3 4 5 6 7

中文翻译

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与MC10E196相关器件

型号	品牌	获取价格	描述	数据表
MC10E196_06	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FN	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FN	MOTOROLA	获取价格	PROGRAMMABLE DELAY CHIP
MC10E196FNG	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FNR2	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FNR2	MOTOROLA	获取价格	Active Delay Line, Programmable, 1-Func, 127-Tap, Complementary Output, ECL, PQCC28, PLAST
MC10E196FNR2G	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E197	ONSEMI	获取价格	DATA SEPARATOR
MC10E197_06	ONSEMI	获取价格	5V ECL Data Separator
MC10E197FN	ONSEMI	获取价格	5V ECL Data Separator