MC10E195

更新时间： 2024-02-05 15:13:39

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
5页	92K
描述
PROGRAMMABLE DELAY CHIP

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中文翻译

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数据手册

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MC10E195 数据手册

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by MC10E195/D

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E195 is a programmable delay chip (PDC) designed

primarily for clock de-skewing and timing adjustment. It provides variable

delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in

the logic symbol. The first two delay elements feature gates that have

been modified to have delays 1.25 and 1.5 times the basic gate delay of

approximately 80 ps. These two elements provide the E195 with a

digitally-selectable resolution of approximately 20 ps. The required

device delay is selected by the seven address inputs D[0:6], which are

latched on chip by a high signal on the latch enable (LEN) control.

PROGRAMMABLE

DELAY CHIP

Because the delay programmability of the E195 is achieved by purely

differential ECL gate delays the device will operate at frequencies of >1.0

GHz while maintaining over 600 mV of output swing.

The E195 thus offers very fine resolution, at very high frequencies, that

is selectable entirely from a digital input allowing for very accurate system

clock timing.

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

An eighth latched input, D7, is provided for cascading multiple PDC’s

for increased programmable range. The cascade logic allows full control

of multiple PDC’s, at the expense of only a single added line to the data

bus for each additional PDC, without the need for any external gating.

• 2.0ns Worst Case Delay Range

• ≈20ps/Delay Step Resolution

• >1.0GHz Bandwidth

NC 18

27 D0

• On Chip Cascade Circuitry

• Extended 100E V

• 75KΩ Input Pulldown Resistors

Range of –4.2 to –5.46V

28 LEN

Pinout:

28-Lead PLCC

(Top View)

CCO

PIN NAMES

Q 14

Q 13

Function

IN/IN

D[0:7]

Q/Q

LEN

SET MIN

SET MAX

CASCADE

Signal Input

Input Enable

Mux Select Inputs

Signal Output

Latch Enable

Min Delay Set

Max Delay Set

Cascade Signal

CCO

NC EN

LOGIC DIAGRAM – SIMPLIFIED

4 GATES

8 GATES

16 GATES

* 1.25

* 1.5

CASCADE

LEN

SET MIN

SET MAX

7 BIT LATCH

LATCH

CASCADE

* DELAYS ARE 25% OR 50% LONGER THAN

* STANDARD (STANDARD

≈ 80 PS)

04/99

REV 3

2–1

Motorola, Inc. 1999

12 3 4 5

中文翻译

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与MC10E195相关器件

型号	品牌	获取价格	描述	数据表
MC10E195_06	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E195FN	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E195FN	MOTOROLA	获取价格	PROGRAMMABLE DELAY CHIP
MC10E195FNG	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E195FNR2	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E195FNR2G	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196	ONSEMI	获取价格	PROGRAMMABLE DELAY CHIP
MC10E196_06	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FN	ONSEMI	获取价格	5V ECL Programmable Delay Chip
MC10E196FN	MOTOROLA	获取价格	PROGRAMMABLE DELAY CHIP

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