MC100LVEL39DW

更新时间： 2024-11-24 05:30:07

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
6页	121K
描述
3.3V ECL ±2/4, ±4/6 Clock Generation Chip

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MC100LVEL39DW 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SOIC-20
针数：	20	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	7.2
其他特性：	NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V	系列：	100LVEL
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	12.8 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	最大频率@ Nom-Sup：	1000000000 Hz
功能数量：	1	反相输出次数：
端子数量：	20	实输出次数：	4
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP20,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	240
电源：	-3.3 V	最大电源电流（ICC）：	61 mA
传播延迟（tpd）：	1.2 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.05 ns	座面最大高度：	2.65 mm
子类别：	Prescaler/Multivibrators	最大供电电压 (Vsup)：	3.8 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	ECL
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn80Pb20)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	7.5 mm	最小 fmax：	1000 MHz
Base Number Matches：	1

MC100LVEL39DW 数据手册

MC100LVEL39

3.3VꢀECL ÷2/4, ÷4/6 Clock

Generation Chip

Description

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by

either a differential or single-ended input signal. In addition, by using

http://onsemi.com

the V output, a sinusoidal source can be AC coupled into the device.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen with

an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip−flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

SO−20 WB

DW SUFFIX

CASE 751D

MARKING DIAGRAM*

Upon startup, the internal flip-flops will attain a random state;

therefore, for systems which utilize multiple LVEL39s, the Master Reset

(MR) input must be asserted to ensure synchronization. For systems

which only use one LVEL39, the MR pin need not be exercised as the

internal divider design ensures synchronization between the ÷2/4 and the

÷4/6 outputs of a single device.

100LVEL39

AWLYYWWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The V pin, an internally generated voltage supply, is available to this

device only. For single-ended input conditions, the unused differential

input is connected to V as a switching reference voltage. V may also

rebias AC coupled inputs. When used, decouple V and V via a

0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When

*For additional marking information, refer to

Application Note AND8002/D.

not used, V should be left open.

Features

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

• 50 ps Maximum Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• ESD Protection: Human Body Model; >2 kV

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range:

• Moisture Sensitivity Level 1

For Additional Information, see Application Note

AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 419 devices

• Pb−Free Packages are Available*

= 3.0 V to 3.8 V with V = 0 V

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.8 V

• Internal Input Pulldown Resistors

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 9

MC100LVEL39/D

12 3 4 5 6

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与MC100LVEL39DW相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL39DWG	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWR2	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWR2G	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL40	ONSEMI	获取价格	Phase-Frequency Detector
MC100LVEL40_06	ONSEMI	获取价格	3.3/5V ECL Differential Phase−Frequency Detector
MC100LVEL40DW	MOTOROLA	获取价格	Phase-Frequency Detector
MC100LVEL40DW	ROCHESTER	获取价格	PHASE DETECTOR, PDSO20, SO-20
MC100LVEL40DW	ONSEMI	获取价格	3.3/5VECL Differential PhaseâFrequency Det
MC100LVEL40DWG	ONSEMI	获取价格	暂无描述
MC100LVEL40DWG	ROCHESTER	获取价格	PHASE DETECTOR, PDSO20, SO-20

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