MC100LVEL40
3.3/5VꢀECL Differential
Phase−Frequency Detector
Description
The MC100LVEL40 is a three state phase frequency−detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V power supply.
When the reference (R) and the feedback (FB) inputs are unequal in
frequency and/or phase the differential up (U) and down (D) outputs
will provide pulse streams which when subtracted and integrated
provide an error voltage for control of a VCO.
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MARKING
DIAGRAM
20
20
100LVEL40
AWLYYWWG
1
The V pin, an internally generated voltage supply, is available to
SO−20
BB
DW SUFFIX
CASE 751D
this device only. For single-ended input conditions, the unused
1
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
For application information, refer to AND8040/D, “Phase Lock
Loop Operation.”
BB
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
The 100 Series Contains Temperature Compensation
Features
*For additional marking information, refer to
Application Note AND8002/D.
• 250 MHz Typical Bandwidth
• PECL Mode Operating Range:
V
CC
= 3.0 V to 5.5 V with V = 0 V
EE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
• NECL Mode Operating Range:
= 0 V with V = −3.0 V to −5.5 V
V
CC
EE
• Internal Input Pulldown Resistor
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC100LVEL40/D