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MC100LVEL56_06 PDF预览

MC100LVEL56_06

更新时间: 2024-09-30 05:30:07
品牌 Logo 应用领域
安森美 - ONSEMI 复用器
页数 文件大小 规格书
7页 120K
描述
3.3V ECL Dual Differential 2:1 Multiplexer

MC100LVEL56_06 数据手册

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MC100LVEL56  
3.3VꢀECL Dual Differential  
2:1 Multiplexer  
Description  
The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The  
differential data path makes the device ideal for multiplexing low skew  
clock or other skew sensitive signals.  
http://onsemi.com  
The device features both individual and common select inputs to  
address both data path and random logic applications.  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs are  
left open the D input will pull down to V , The D input will bias  
EE  
around V /2 forcing the Q output LOW.  
CC  
SO20 WB  
DW SUFFIX  
CASE 751D  
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
V
may also rebias AC coupled inputs. When used, decouple V and  
via a 0.01 mF capacitor and limit current sourcing or sinking to  
BB  
BB  
CC  
MARKING DIAGRAM*  
0.5 mA. When not used, V should be left open.  
BB  
Features  
20  
580 ps Typical Propagation Delays  
Separate and Common Select  
The 100 Series Contains Temperature Compensation  
PECL Mode Operating Range:  
100LVEL56  
AWLYYWWG  
V
= 3.0 V to 3.8 V with V = 0 V  
1
CC  
EE  
NECL Mode Operating Range:  
= 0 V with V = 3.0 V to 3.8 V  
Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL  
Q Output will Default LOW with Inputs Open or at V  
PbFree Packages are Available*  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
V
CC  
EE  
WL  
YY  
WW  
G
EE  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 11  
MC100LVEL56/D  

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