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MC100LVEL51 PDF预览

MC100LVEL51

更新时间: 2024-11-23 22:58:07
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
3页 86K
描述
Differential Clock D Flip-Flop

MC100LVEL51 数据手册

 浏览型号MC100LVEL51的Datasheet PDF文件第2页浏览型号MC100LVEL51的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC100LVEL51 is a differential clock D flip-flop with reset. The  
device is functionally equivalent to the EL51 device, but operates from a  
low voltage supply. With propagation delays and output transition times  
essentially equal to the EL51, the LVEL51 is ideally suited for those  
applications which require the ultimate in AC performance at 3.3V V  
.
CC  
The reset input is an asynchronous, level triggered signal. Data enters  
the master portion of the flip-flop when the clock is LOW and is  
transferred to the slave, and thus the outputs, upon a positive transition of  
the clock. The differential clock inputs of the LVEL51 allow the device to  
be used as a negative edge triggered flip-flop.  
The differential input employs clamp circuitry to maintain stability under  
open input conditions. When left open, the CLK input will be pulled down  
8
to V  
and the CLK input will be biased at V /2.  
EE  
CC  
1
475ps Propagation Delay  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751-05  
2.8GHz Toggle Frequency  
Operates from –3.3V (or 3.3V) Supply  
75kInternal Input Pulldown Resistors  
>2000V ESD Protection  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
R 1  
8
7
V
CC  
TRUTH TABLE  
R
D
L
R
L
CLK  
Z
Q
L
D
2
3
D
Q
Q
Flip-Flop  
H
X
L
Z
H
L
CLK  
6
5
H
X
Z = LOW to HIGH Transition  
CLK  
4
V
EE  
8/96  
Motorola, Inc. 1996  
REV 1  

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