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MC100LVEL51DTG PDF预览

MC100LVEL51DTG

更新时间: 2024-11-24 04:40:19
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
8页 141K
描述
3.3V ECL Differential Clock D Flip-Flop

MC100LVEL51DTG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:LEAD FREE, PLASTIC, TSSOP-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.67
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -3.8V系列:100LVEL
JESD-30 代码:S-PDSO-G8JESD-609代码:e3
长度:3 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:2900000000 Hz湿度敏感等级:3
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:-3.3 V
最大电源电流(ICC):37 mAProp。Delay @ Nom-Sup:0.55 ns
传播延迟(tpd):0.52 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):3.8 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:3 mm最小 fmax:2800 MHz
Base Number Matches:1

MC100LVEL51DTG 数据手册

 浏览型号MC100LVEL51DTG的Datasheet PDF文件第2页浏览型号MC100LVEL51DTG的Datasheet PDF文件第3页浏览型号MC100LVEL51DTG的Datasheet PDF文件第4页浏览型号MC100LVEL51DTG的Datasheet PDF文件第5页浏览型号MC100LVEL51DTG的Datasheet PDF文件第6页浏览型号MC100LVEL51DTG的Datasheet PDF文件第7页 
MC100LVEL33  
3.3VꢀECL ÷4 Divider  
Description  
The MC100LVEL33 is an integrated ÷4 divider. The LVEL is  
functionally equivalent to the EL33 and works from a 3.3 V supply.  
The reset pin is asynchronous and is asserted on the rising edge.  
Upon power-up, the internal flip-flops will attain a random state; the  
reset allows for the synchronization of multiple LVEL33’s in a system.  
http://onsemi.com  
MARKING  
The V pin, an internally generated voltage supply, is available to  
BB  
DIAGRAMS*  
this device only. For single-ended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
8
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
8
1
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
KVL33  
ALYW  
G
to 0.5 mA. When not used, V should be left open.  
BB  
SOIC8  
D SUFFIX  
CASE 751  
Features  
1
8
630 ps Typical Propagation Delay  
4.0 GHz Typical Maximum Frequency  
ESD Protection: >4 kV Human Body Model,  
>200 V Machine Model  
8
1
KV33  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
The 100 Series Contains Temperature Compensation  
G
1
PECL Mode Operating Range: V = 3.0 V to 3.8 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 3.0 V to 3.8 V  
EE  
Internal Input Pulldown Resistors  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
1
4
DFN8  
Moisture Sensitivity Level 1  
MN SUFFIX  
CASE 506AA  
For Additional Information, see Application Note AND8003/D  
Flammability Rating: UL 94 V0 @ 0.125 in,  
Oxygen Index: 28 to 34  
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
Transistor Count = 130 devices  
W = Work Week  
M = Date Code  
PbFree Packages are Available  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 4  
MC100LVEL33/D  

MC100LVEL51DTG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP35DTG ONSEMI

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MC100LVEL51DTR2G ONSEMI

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3.3V ECL Differential Clock D Flip-Flop

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