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MC100EP35DTR2G PDF预览

MC100EP35DTR2G

更新时间: 2024-11-25 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 158K
描述
3.3V / 5V ECL JK Flip−Flop

MC100EP35DTR2G 数据手册

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MC10EP35, MC100EP35  
3.3V / 5VꢀECL JK Flip−Flop  
Description  
The MC10/100EP35 is a higher speed/low voltage version of the  
EL35 JK flipflop. The J/K data enters the master portion of the  
flipflop when the clock is LOW and is transferred to the slave, and  
thus the outputs, upon a positive transition of the clock. The reset pin is  
asynchronous and is activated with a logic HIGH.  
http://onsemi.com  
The 100 Series contains temperature compensation.  
MARKING  
DIAGRAMS*  
Features  
410 ps Propagation Delay  
Maximum Frequency > 3 GHz Typical  
8
1
8
8
HEP35  
ALYW  
KEP35  
ALYW  
G
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
1
CC  
G
with V = 0 V  
SOIC8  
D SUFFIX  
CASE 751  
EE  
1
NECL Mode Operating Range: V = 0 V  
CC  
with V = 3.0 V to 5.5 V  
EE  
Open Input Default State  
Q Output Will Default LOW with Inputs Open or at V  
PbFree Packages are Available  
8
1
8
1
8
EE  
1
HP35  
KP35  
ALYWG  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
G
G
1
4
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
H
K
= MC10  
= MC100  
A
L
= Assembly Location  
= Wafer Lot  
5R = MC10  
3M = MC100  
Y
W
M
G
= Year  
= Work Week  
= Date Code  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 5  
MC10EP35/D  

MC100EP35DTR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC10EP35DTR2G ONSEMI

类似代替

3.3V / 5V ECL JK Flip−Flop
MC100LVEL51DTG ONSEMI

类似代替

3.3V ECL Differential Clock D Flip-Flop

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