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MC100EP446FAR2 PDF预览

MC100EP446FAR2

更新时间: 2024-11-26 22:15:27
品牌 Logo 应用领域
安森美 - ONSEMI 转换器移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
20页 176K
描述
3.3V/5V 8々Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter

MC100EP446FAR2 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, LQFP-32
针数:32Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.62
Is Samacsys:N其他特性:ECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
计数方向:RIGHT系列:100E
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
湿度敏感等级:2位数:8
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
传播延迟(tpd):1.025 ns认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:NEGATIVE EDGE宽度:7 mm
最小 fmax:3200 MHzBase Number Matches:1

MC100EP446FAR2 数据手册

 浏览型号MC100EP446FAR2的Datasheet PDF文件第2页浏览型号MC100EP446FAR2的Datasheet PDF文件第3页浏览型号MC100EP446FAR2的Datasheet PDF文件第4页浏览型号MC100EP446FAR2的Datasheet PDF文件第5页浏览型号MC100EP446FAR2的Datasheet PDF文件第6页浏览型号MC100EP446FAR2的Datasheet PDF文件第7页 
MC10EP446, MC100EP446  
3.3V/5V 8-Bit  
CMOS/ECL/TTL Data Input  
Parallel/Serial Converter  
The MC10/100EP446 is an integrated 8−bit parallel to serial data  
converter. The device is designed with unique circuit topology to  
operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence  
from parallel data into a serial data stream is from bit D0 to D7. The  
parallel input pins D0−D7 are configurable to be threshold controlled by  
CMOS, ECL, or TTL level signals. The serial data rate output can be  
selected at internal clock data rate or twice the internal clock data rate  
using the CKSEL pin.  
http://onsemi.com  
MARKING DIAGRAM*  
Control pins are provided to reset (SYNC) and disable internal clock  
circuitry (CKEN). In either CKSEL modes, the internal flip−flops are  
triggered on the rising edge for CLK and the multiplexers are switched  
on the falling edge of CLK, therefore, all associated specification  
limits are referenced to the negative edge of the clock input.  
MCXXX  
EP446  
AWLYYWW  
LQFP−32  
FA SUFFIX  
CASE 873A  
32  
Additionally, V pin is provided for single−ended input condition.  
BB  
1
The 100 Series devices contain temperature compensation network.  
XXX  
A
WL  
YY  
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
3.2 Gb/s Typical Data Rate Capability  
Differential Clock and Serial Outputs  
V Output for Single-ended Input Applications  
BB  
WW  
Asynchronous Data Reset (SYNC)  
PECL Mode Operating Range:  
*For additional marking information, refer to  
Application Note AND8002/D.  
V
= 3.0 V to 5.5 V with V = 0 V  
CC  
EE  
NECL Mode Operating Range:  
= 0 V with V = −3.0 V to −5.5 V  
V
CC  
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
Open Input Default State  
dimensions section on page 17 of this data sheet.  
Safety Clamp on Inputs  
Parallel Interface Can Support PECL, TTL or CMOS  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 5  
MC10EP446/D  

MC100EP446FAR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP446FAR2G ONSEMI

完全替代

3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter
MC100EP446FA ONSEMI

完全替代

3.3V/5V 8々Bit CMOS/ECL/TTL Data Input Paralle

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