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MC100EP52 PDF预览

MC100EP52

更新时间: 2024-01-17 13:04:22
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器触发器时钟
页数 文件大小 规格书
10页 86K
描述
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Data and Clock D Flip-Flop

MC100EP52 技术参数

是否无铅:不含铅生命周期:Active
零件包装代码:SOIC包装说明:TSSOP, TSSOP8,.19
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.64Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列:100E
JESD-30 代码:S-PDSO-G8JESD-609代码:e3
长度:3 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:4000000000 Hz湿度敏感等级:3
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:-4.5 V
最大电源电流(ICC):47 mAProp。Delay @ Nom-Sup:0.41 ns
传播延迟(tpd):0.38 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:3 mmBase Number Matches:1

MC100EP52 数据手册

 浏览型号MC100EP52的Datasheet PDF文件第2页浏览型号MC100EP52的Datasheet PDF文件第3页浏览型号MC100EP52的Datasheet PDF文件第4页浏览型号MC100EP52的Datasheet PDF文件第5页浏览型号MC100EP52的Datasheet PDF文件第6页浏览型号MC100EP52的Datasheet PDF文件第7页 
MC10EP52, MC100EP52  
3.3V / 5VꢀECL Differential  
Data and Clock D Flip−Flop  
The MC10EP/100EP52 is a differential data, differential clock D  
flip−flop. The device is pin and functionally equivalent to the EL52  
device.  
Data enters the master portion of the flip−flop when the clock is  
LOW and is transferred to the slave, and thus the outputs, upon a  
positive transition of the clock. The differential clock inputs of the  
EP52 allow the device to also be used as a negative edge triggered  
device.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
8
The EP52 employs input clamping circuitry so that under open input  
8
HEP52  
ALYW  
KEP52  
ALYW  
conditions (pulled down to V ) the outputs of the device will remain  
1
EE  
stable.  
SO−8  
D SUFFIX  
CASE 751  
The 100 Series contains temperature compensation.  
1
1
330 ps Typical Propagation Delay  
8
1
8
1
Maximum Frequency u 4 GHz Typical  
PECL Mode: V = 3.0 V to 5.5 V with V = 0 V  
8
HP52  
ALYW  
KP52  
ALYW  
CC  
EE  
1
TSSOP−8  
DT SUFFIX  
CASE 948R  
NECL Mode: V = 0 V with V = −3.0 V to −5.5 V  
CC  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
EE  
L = Wafer Lot  
Y = Year  
H = MC10  
K = MC100  
W = Work Week  
A = Assembly Location  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 3  
MC10EP52/D  

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