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MC100EP451 PDF预览

MC100EP451

更新时间： 2024-02-01 18:40:48
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 94K
描述
3.3V / 5VECL 6-Bit Differential Register with Master Reset

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中文翻译

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MC100EP451 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC32,.2SQ,20
针数：32Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.06
其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V计数方向：RIGHT
系列：100EJESD-30 代码：S-PQCC-N32
JESD-609代码：e3长度：5 mm
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：3000000000 Hz
湿度敏感等级：1位数：6
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC32,.2SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：-4.5 V
传播延迟（tpd）：0.55 ns认证状态：Not Qualified
座面最大高度：1 mm子类别：Shift Registers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40触发器类型：POSITIVE EDGE
宽度：5 mmBase Number Matches：1

MC100EP451 数据手册

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MC10EP451, MC100EP451  
3.3V / 5VꢀECL 6−Bit  
Differential Register with  
Master Reset  
The MC10/100EP451 is a 6−bit fully differential register with  
common clock and single−ended Master Reset (MR). It is ideal for  
very high frequency applications where a registered data path is  
necessary.  
http://onsemi.com  
MARKING  
DIAGRAM*  
All inputs have a 75 kW pulldown resistor internally. Differential  
inputs have an override clamp. Unused differential register inputs can  
be left open and will default LOW. When the differential inputs are  
forced to < V + 1.2 V, the clamp will override and force the output to  
EE  
a default state. When in the default state, and since the flip−flop is edge  
triggered, the output reaches a determined, but not predicted, valid  
state.  
The positive transition of CLK (pin 4) will latch the registers.  
Master Reset (MR) HIGH will asynchronously reset all registers  
forcing Q outputs to go LOW.  
MCxxx  
EP451  
AWLYYWW  
LQFP−32  
FA SUFFIX  
CASE 873A  
32  
1
The 100 Series contains temperature compensation.  
xxx = 10 or 100  
= Assembly Location  
WL = Wafer Lot  
YY = Year  
• 450 ps Typical Propagation Delay  
• Maximum Frequency > 3.0 GHz Typical  
• Asynchronous Master Reset  
A
WW = Work Week  
• 20 ps Skew Within Device, 35 ps Skew Device−To−Device  
*For additional marking information, refer to  
Application Note AND8002/D.  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
With V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
With V = −3.0 V to −5.5 V  
EE  
• Open Input Default State  
• Safety Clamp on Inputs  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 6  
MC10EP451/D  
1234567...10

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