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MC100EP445FAR2 PDF预览

MC100EP445FAR2

更新时间: 2024-09-27 22:18:07
品牌 Logo 应用领域
安森美 - ONSEMI 转换器
页数 文件大小 规格书
16页 119K
描述
3.3V/5VECL 8-Bit Serial/Parallel Converter

MC100EP445FAR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:32
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.49其他特性:ECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
计数方向:RIGHT系列:100E
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
湿度敏感等级:2位数:8
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
传播延迟(tpd):1.795 ns认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:7 mm
最小 fmax:2800 MHzBase Number Matches:1

MC100EP445FAR2 数据手册

 浏览型号MC100EP445FAR2的Datasheet PDF文件第2页浏览型号MC100EP445FAR2的Datasheet PDF文件第3页浏览型号MC100EP445FAR2的Datasheet PDF文件第4页浏览型号MC100EP445FAR2的Datasheet PDF文件第5页浏览型号MC100EP445FAR2的Datasheet PDF文件第6页浏览型号MC100EP445FAR2的Datasheet PDF文件第7页 
MC10EP445, MC100EP445  
3.3V/5VꢀECL 8−Bit  
Serial/Parallel Converter  
The MC10/100EP445 is an integrated 8–bit differential serial to  
parallel data converter with asynchronous data synchronization. The  
device has two modes of operation. CKSEL HIGH mode is designed  
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode  
is designed to operate at twice the internal clock data rate of up to  
5.0 Gb/s. The conversion sequence was chosen to convert the first  
serial bit to Q0, the second bit to Q1, etc. Two selectable differential  
serial inputs, which are selected by SINSEL, provide this device with  
loop-back testing capability. The MC10/100EP445 has a SYNC pin  
which, when held high for at least two consecutive clock cycles, will  
swallow one bit of data shifting the start of the conversion data from  
http://onsemi.com  
MARKING  
DIAGRAM*  
MCXXX  
EP445  
AWLYYWW  
D to D . Each additional shift requires an additional pulse to be  
n
n+1  
LQFP-32  
FA SUFFIX  
CASE 873A  
applied to the SYNC pin.  
Control pins are provided to reset and disable internal clock  
32  
circuitry. Additionally, V pin is provided for single-ended input  
1
BB  
condition.  
XXX = 10 OR 100  
The 100 Series contains temperature compensation.  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
300 ps Propagation Delay  
5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode  
Differential Clock and Serial Inputs  
*For additional information, see Application Note  
AND8002/D  
V Output for Single-Ended Input Applications  
BB  
Asynchronous Data Synchronization (SYNC)  
Asynchronous Master Reset (RESET)  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
ORDERING INFORMATION  
CC  
with V = -3.0 V to -5.5 V  
EE  
Device  
Package  
Shipping  
Open Input Default State  
MC10EP445FA  
LQFP-32  
250 Units/Tray  
CLK ENABLE Immune to Runt Pulse Generation  
MC10EP445FAR2 LQFP-32 2000/Tape & Reel  
MC100EP445FA LQFP-32 250 Units/Tray  
MC100EP445FAR2 LQFP-32 2000/Tape & Reel  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
November, 2002 - Rev. 7  
MC10EP445/D  

MC100EP445FAR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP445FAR2G ONSEMI

完全替代

3.3V/5V ECL 8−Bit Serial/Parallel Converter
MC100EP445FA ONSEMI

完全替代

3.3V/5VECL 8-Bit Serial/Parallel Converter
MC10EP445FA ONSEMI

完全替代

3.3V/5VECL 8-Bit Serial/Parallel Converter

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