MC100LVEL33
3.3VꢀECL ÷4 Divider
Description
The MC100LVEL33 is an integrated ÷4 divider. The LVEL is
functionally equivalent to the EL33 and works from a 3.3 V supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple LVEL33’s in a system.
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MARKING
The V pin, an internally generated voltage supply, is available to
BB
DIAGRAMS*
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
8
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
8
1
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
KVL33
ALYW
G
to 0.5 mA. When not used, V should be left open.
BB
SOIC−8
D SUFFIX
CASE 751
Features
1
8
• 630 ps Typical Propagation Delay
• 4.0 GHz Typical Maximum Frequency
• ESD Protection: >4 kV Human Body Model,
>200 V Machine Model
8
1
KV33
ALYWG
TSSOP−8
DT SUFFIX
CASE 948R
• The 100 Series Contains Temperature Compensation
G
1
• PECL Mode Operating Range: V = 3.0 V to 3.8 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −3.8 V
EE
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1
4
DFN8
• Moisture Sensitivity Level 1
MN SUFFIX
CASE 506AA
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
A
L
Y
= Assembly Location
= Wafer Lot
= Year
• Transistor Count = 130 devices
W = Work Week
M = Date Code
• Pb−Free Packages are Available
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 4
MC100LVEL33/D