MC100LVEL38DW

更新时间： 2024-11-23 22:58:07

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器时钟发生器逻辑集成电路光电二极管输出元件
页数	文件大小	规格书
5页	131K
描述
±2, ±4/6 Clock Generation Chip

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技术参数
数据手册

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MC100LVEL38DW 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.42	Is Samacsys：	N
其他特性：	WITH DIFFERENTIAL OUTPUT; CAN BE OPERATED FROM +VE SUPPLY ALSO; MAX PART TO PART SKEW = 0.24NS	系列：	100LVEL
输入调节：	DIFFERENTIAL	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	12.8 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	最大I（ol）：	0.1 A
功能数量：	1	反相输出次数：
端子数量：	20	实输出次数：	5
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	OPEN-EMITTER	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	-3.3 V	最大电源电流（ICC）：	65 mA
传播延迟（tpd）：	1.1 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.075 ns	座面最大高度：	2.65 mm
子类别：	Clock Drivers	表面贴装：	YES
技术：	ECL	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	最小 fmax：	1000 MHz
Base Number Matches：	1

MC100LVEL38DW 数据手册

SEMICONDUCTOR TECHNICAL DATA

÷ ÷

The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but

is specified for operation at the standard 100K ECL voltage supply. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single-ended LVECL or, if positive power supplies are

used, LVPECL input signal. In addition, by using the V

sinusoidal source can be AC coupled into the device (see Interfacing

section of the ECLinPS Data Book DL140/D). If a single-ended input is

output, a

to be used, the V

output should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. The V

output is designed to

act as the switching reference for the input of the LVEL38 under

single-ended input conditions, as a result, this pin can only source/sink up

to 0.5mA of current.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

The Phase_Out output will go HIGH for one clock cycle whenever the

÷2 and the ÷4/6 outputs are both transitioning from a LOW to a HIGH.

This output allows for clock synchronization within the system.

PIN DESCRIPTION

FUNCTION

Upon startup, the internal flip-flops will attain a random state; therefore,

for systems which utilize multiple LVEL38s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one LVEL38, the MR pin need not be exercised as the internal divider

design ensures synchronization between the ÷2 and the ÷4/6 outputs of a

single device.

CLK

Diff Clock Inputs

Sync Enable

Master Reset

Reference Output

Diff ÷2 Outputs

Diff ÷4/6 Outputs

Frequency Select Input

Q , Q

DIVSEL

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 75kΩ Internal Input Pulldown Resistors

• >1500V ESD Protection

Phase_Out

Phase Sync Signal

FUNCTION TABLE

CLK

FUNCTION

• Low Voltage V

Range of –3.0 to –3.8V

Divide

Hold Q

0–3

Reset Q

Pinout: 20-Lead SOIC (Top View)

0–3

Z = Low-to-High Transition

ZZ = High-to-Low Transition

DIVSEL

Q , Q OUTPUTS

2 3

Divide by 4

Divide by 6

EN DIV_SEL CLK CLK

10/94

Motorola, Inc. 1996

REV 1

4–1

12 3 4 5

中文翻译

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与MC100LVEL38DW相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL38DWG	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DWR2	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DWR2G	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL39	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100LVEL39	ONSEMI	获取价格	±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DW	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100LVEL39DW	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWG	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWR2	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWR2G	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip

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