MC100LVEL39

更新时间： 2024-11-23 22:58:07

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
4页	130K
描述
±2/4, ±4/6 Clock Generation Chip

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数据手册

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MC100LVEL39 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but

is specified for operation at the standard 100K ECL voltage supply. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single-ended LVECL or, if positive power supplies are

used, LVPECL input signal. In addition, by using the V

sinusoidal source can be AC coupled into the device (see Interfacing

section of the ECLinPS Data Book DL140/D). If a single-ended input is

output, a

to be used, the V

output should be connected to the CLK input and

bypassed to ground via a 0.01µF capacitor. The V

output is designed to

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

act as the switching reference for the input of the LVEL39 under

single-ended input conditions, as a result, this pin can only source/sink up

to 0.5mA of current.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

PIN DESCRIPTION

FUNCTION

CLK

Diff Clock Inputs

Sync Enable

Master Reset

Upon startup, the internal flip-flops will attain a random state; therefore,

for systems which utilize multiple LVEL39s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one LVEL39, the MR pin need not be exercised as the internal divider

design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of

a single device.

Reference Output

Diff ÷2/4 Outputs

Diff ÷4/6 Outputs

Frequency Select Input

Q , Q

DIVSEL

FUNCTION TABLE

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 75kΩ Internal Input Pulldown Resistors

• >2000V ESD Protection

CLK

FUNCTION

Divide

Hold Q

0–3

Reset Q

0–3

Z = Low-to-High Transition

ZZ = High-to-Low Transition

• Low Voltage V

Range of –3.0 to –3.8V

DIVSELa

Q , Q OUTPUTS

0 1

Pinout: 20-Lead SOIC (Top View)

Divide by 2

Divide by 4

DIVSELb

Q , Q OUTPUTS

2 3

Divide by 4

Divide by 6

EN DIVSELb CLK CLK

NC DIVSELa

3/96

Motorola, Inc. 1996

REV 2

4–1

12 3 4

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与MC100LVEL39相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL39DW	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100LVEL39DW	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWG	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWR2	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWR2G	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL40	ONSEMI	获取价格	Phase-Frequency Detector
MC100LVEL40_06	ONSEMI	获取价格	3.3/5V ECL Differential Phase−Frequency Detector
MC100LVEL40DW	MOTOROLA	获取价格	Phase-Frequency Detector
MC100LVEL40DW	ROCHESTER	获取价格	PHASE DETECTOR, PDSO20, SO-20
MC100LVEL40DW	ONSEMI	获取价格	3.3/5VECL Differential PhaseâFrequency Det

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