Datasheet > MC100LVEL38_06

MC100LVEL38_06

更新时间： 2024-11-24 05:30:07

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
7页	123K
描述
3.3V ECL ±2, ±4/6 Clock Generation Chip

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MC100LVEL38_06 数据手册

MC100LVEL38

3.3VꢀECL ÷2, ÷4/6 Clock

Generation Chip

Description

The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either a

differential or single-ended input signal.

http://onsemi.com

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as can happen with an

asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

SO−20 WB

DW SUFFIX

CASE 751D

MARKING DIAGRAM*

The Phase_Out output will go HIGH for one clock cycle whenever

the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a

HIGH. This output allows for clock synchronization within the system.

Upon startup, the internal flip-flops will attain a random state; therefore,

for systems which utilize multiple LVEL38s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one LVEL38, the MR pin need not be exercised as the internal divider

design ensures synchronization between the ÷2 and the ÷4/6 outputs of a

single device.

100LVEL38

AWLYYWWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

*For additional marking information, refer to

Application Note AND8002/D.

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

Features

• 50 ps Maximum Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• ESD Protection: >2 kV Human Body Model

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range:

• Moisture Sensitivity Level 1

= 3.0 V to 3.8 V with V = 0 V

For Additional Information, see Application Note

AND8003/D

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −3.8 V

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 388 devices

• Pb−Free Packages are Available*

• Internal Input 75 kW Pulldown Resistors

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 8

MC100LVEL38/D

12 3 4 5 6 7

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与MC100LVEL38_06相关器件

型号	品牌	获取价格	描述	数据表
MC100LVEL38DW	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DW	MOTOROLA	获取价格	±2, ±4/6 Clock Generation Chip
MC100LVEL38DWG	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DWR2	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL38DWR2G	ONSEMI	获取价格	3.3V ECL ±2, ±4/6 Clock Generation Chip
MC100LVEL39	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100LVEL39	ONSEMI	获取价格	±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DW	MOTOROLA	获取价格	±2/4,±4/6 Clock Generation Chip
MC100LVEL39DW	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip
MC100LVEL39DWG	ONSEMI	获取价格	3.3V ECL ±2/4, ±4/6 Clock Generation Chip

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