Datasheet > MC100LVEL37DW

MC100LVEL37DW

更新时间： 2024-11-23 22:58:07

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
3页	76K
描述
1:4 ±1/±2 ECL/PECL Clock Fanout Buffer

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MC100LVEL37DW 数据手册

SEMICONDUCTOR TECHNICAL DATA

÷ ÷

The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device

offers two outputs at ÷1 of the input frequrency, and two outputs at ÷2 of

the input frequency. The Low Output–Output Skew of the device makes it

ideal for distributing1x and 1/2x frequency synchronous signals.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs are left

open the D input will pull down to V , The D input will bias around V /2

and the Q output will go LOW.

DW SUFFIX

20–LEAD PLASTIC SOIC WIDE PACKAGE

CASE 751D–04

• Differential Inputs and Outputs

• 20–Lead SOIC Packaging

• 700ps Typical Propagation Delays

• 50ps Output–Output Skews

• Low Voltage 100K ECL

• >2000V ESD Protection

PIN NAMES

Pins

Function

Qna, Qna

CLKn, CLKn

Clk_Sel

Differential Clock Outputs

Differential Clock Inputs

Input Clock Selection

÷1

÷2

‘0’ Selects CLK0; ‘1‘ Selects CLK1

Asynchronous Master Reset

‘1’ Resets Dividers

VCC CLK0 CLK0 Clk_Sel CLK1 CLK1 MR

VEE

Figure 1. 20–Lead Pinout (Top View)

MC100LVEL37

DC CHARACTERISTICS (V

= –3.0V to –3.8V; V

= GND)

–40°C

0°C

Typ

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Max

Min

Typ

Max

Min

Typ

Max Unit

Power Supply Current

Input HIGH Current

Input LOW Current

150

µA

CLKn

CLKn –300

0.5

–300

0.5

–300

0.5

–300

INL

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.

5/97

REV 0

4–1

Motorola, Inc. 1997

12 3

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