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MC100EP139DTR2 PDF预览

MC100EP139DTR2

更新时间： 2024-02-24 16:13:23
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器时钟发生器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 143K
描述
±2/4, ±4./5/6 Clock Generation Chip

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中文翻译

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MC100EP139DTR2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.15其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列：100E输入调节：DIFFERENTIAL
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：20实输出次数：4
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：-3.0/-5.5/3.3/5.0 VProp。Delay @ Nom-Sup：1.1 ns
传播延迟（tpd）：0.9 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.1 ns座面最大高度：1.2 mm
子类别：Clock Drivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：4.4 mm最小 fmax：1000 MHz
Base Number Matches：1

MC100EP139DTR2 数据手册

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The MC100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip  
designed explicitly for low skew clock generation applications. The  
internal dividers are synchronous to each other, therefore, the common  
output edges are all precisely aligned. The device can be driven by  
either a differential or single–ended ECL or, if positive power supplies  
http://onsemi.com  
are used, LVPECL input signals. In addition, by using the V output,  
BB  
a sinusoidal source can be AC coupled into the device. If a  
single–ended input is to be used, the V  
output should be connected  
BB  
TSSOP–20  
DT SUFFIX  
CASE 948E  
SO–20  
DW SUFFIX  
CASE 751D  
to the CLK input and bypassed to ground via a 0.01µF capacitor.  
The common enable (EN) is synchronous so that the internal  
dividers will only be enabled/disabled when the internal clock is  
already in the LOW state. This avoids any chance of generating a runt  
clock pulse on the internal clock when the device is enabled/disabled  
as can happen with an asynchronous control. The internal enable  
flip–flop is clocked on the falling edge of the input clock, therefore, all  
associated specification limits are referenced to the negative edge of  
the clock input.  
Upon startup, the internal flip–flops will attain a random state;  
therefore, for systems which utilize multiple EP139s, the master reset  
(MR) input must be asserted to ensure synchronization. For systems  
which only use one EP139, the MR pin need not be exercised as the  
internal divider design ensures synchronization between the ÷2/4 and  
MARKING DIAGRAM  
KEP  
139  
ALYW  
MC100EP139  
AWLYWW  
A = Assembly Location  
L = Wafer Lot  
Y = Year  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
the ÷4/5/6 outputs of a single device. All V  
externally connected to power supply to guarantee proper operation.  
and V pins must be  
CC  
EE  
W = Work Week  
WW= Work Week  
*For additional information, see Application Note  
AND8002/D  
• 50ps Output–to–Output Skew  
• PECL mode: 3.0V to 5.5V V  
with V = 0V  
EE  
CC  
• ECL mode: 0V V  
CC  
with V = –3.0V to –5.5V  
EE  
• Synchronous Enable/Disable  
• Master Reset for Synchronization of Multiple Chips  
• Q Output will default LOW with inputs open or at V  
• ESD Protection: >2KV HBM, >100V MM  
EE  
ORDERING INFORMATION  
• V Output  
BB  
Device  
Package  
TSSOP  
TSSOP  
SOIC  
Shipping  
75 Units/Rail  
2500 Tape/Reel  
38 Units/Rail  
2500 Tape/Reel  
• New Differential Input Common Mode Range  
• Moisture Sensitivity Level 2  
For Additional Information, See Application Note AND8003/D  
• Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
MC100EP139DT  
MC100EP139DTR2  
MC100EP139DW  
MC100EP139DWR2  
SOIC  
• Transistor Count = 758 devices  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
December, 1999 – Rev. 1  
MC100EP139/D  
12345678

中文翻译

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MC100EP139DTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP139DTR2G ONSEMI

完全替代

 3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation C

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