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MC100EP139MNTXG

更新时间： 2024-01-23 04:55:01
品牌 Logo 应用领域
安森美 - ONSEMI 时钟发生器
页数 文件大小 规格书
14页 192K
描述
3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation Chip

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MC100EP139MNTXG 数据手册

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MC10EP139, MC100EP139  
3.3V / 5VꢀECL ÷2/4, ÷4/5/6  
Clock Generation Chip  
Description  
The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip  
designed explicitly for low skew clock generation applications. The  
internal dividers are synchronous to each other, therefore, the common  
output edges are all precisely aligned. The device can be driven by either  
a differential or single−ended ECL or, if positive power supplies are used,  
http://onsemi.com  
MARKING  
DIAGRAMS*  
LVPECL input signals. In addition, by using the V output, a sinusoidal  
BB  
source can be AC coupled into the device. If a single−ended input is to be  
HEP or KEP  
used, the V output should be connected to the CLK input and bypassed  
to ground via a 0.01 mF capacitor.  
BB  
139  
ALYWG  
G
1
The common enable (EN) is synchronous so that the internal dividers  
will only be enabled/disabled when the internal clock is already in the  
LOW state. This avoids any chance of generating a runt clock pulse on  
the internal clock when the device is enabled/disabled as can happen with  
an asynchronous control. The internal enable flip−flop is clocked on the  
falling edge of the input clock, therefore, all associated specification  
limits are referenced to the negative edge of the clock input.  
TSSOP−20  
DT SUFFIX  
CASE 948E  
20  
MCXXXEP139  
AWLYYWWG  
1
Upon start−up, the internal flip−flops will attain a random state;  
therefore, for systems which utilize multiple EP139s, the master reset  
(MR) input must be asserted to ensure synchronization. For systems  
which only use one EP139, the MR pin need not be exercised as the  
internal divider design ensures synchronization between the ÷2/4 and the  
SOIC−20  
DW SUFFIX  
CASE 751D  
1
20  
÷4/5/6 outputs of a single device. All V  
and V pins must be  
1
CC  
EE  
XXXX  
externally connected to power supply to guarantee proper operation.  
The 100 Series contains temperature compensation.  
EP139  
ALYWG  
G
QFN−20  
MN SUFFIX  
CASE 485E  
Features  
• Maximum Frequency > 1.0 GHz Typical  
• 50 ps Output−to−Output Skew  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
HEP  
KEP  
XXX  
A
L,WL  
Y, YY  
= MC10EP  
with V = 0 V  
= MC100EP  
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
• Open Input Default State  
W, WW = Work Week  
• Safety Clamp on Inputs  
G or G = Pb−Free Package  
• Synchronous Enable/Disable  
(Note: Microdot may be in either location)  
• Master Reset for Synchronization of Multiple Chips  
*For additional marking information, refer to  
Application Note AND8002/D.  
• V Output  
BB  
• Pb−Free Packages are Available  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 11 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 7  
MC10EP139/D  
1234567...14

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