Datasheet > MC100EP14_06

MC100EP14_06

更新时间： 2024-11-20 05:22:27

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
9页	132K
描述
3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

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MC100EP14_06 数据手册

MC100EP14

3.3V / 5Vꢀ1:5 Differential

ECL/PECL/HSTL Clock Driver

Description

The MC100EP14 is a low skew 1−to−5 differential driver, designed with

clock distribution in mind, accepting two clock sources into an input

multiplexer. The ECL/PECL input signals can be either differential or

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single−ended (if the V output is used). HSTL inputs can be used when

the LVEP14 is operating under PECL conditions.

The EP14 specifically guarantees low output−to−output skew. Optimal

design, layout, and processing minimize skew within a device and from

device to device.

To ensure that the tight skew specification is realized, both sides of

any differential output need to be terminated even if only one output is

being used. If an output pair is unused, both outputs may be left open

(unterminated) without affecting skew.

TSSOP−20

DT SUFFIX

CASE 948E

The common enable (EN) is synchronous, outputs are enabled/

disabled in the LOW state. This avoids a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. The internal flip flop is clocked on the falling edge of the input

clock, therefore all associated specification limits are referenced to the

negative edge of the clock input.

MARKING DIAGRAM*

100

EP14

ALYWG

The MC100EP14, as with most other ECL devices, can be operated

from a positive V supply in PECL mode. This allows the EP14 to be

used for high performance clock distribution in 5.0 V systems.

Designers can take advantage of the EP14’s performance to distribute

low skew clocks across the backplane or the board.

= Assembly Location

= Wafer Lot

= Year

Features

• 400 ps Typical Propagation Delay

• 100 ps Device−to−Device Skew

• 25 ps Within Device Skew

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

• Maximum Frequency > 2 GHz Typical

• The 100 Series Contains Temperature Compensation

• PECL and HSTL Mode:

*For additional marking information, refer to

Application Note AND8002/D.

= 3.0 V to 5.5 V with V = 0 V

• NECL Mode:

= 0 V with V = −3.0 V to −5.5 V

• Open Input Default State

• These are Pb−Free Devices

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 5

MC100EP14/D

12 3 4 5 6 7...9

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与MC100EP14_06相关器件

型号	品牌	获取价格	描述	数据表
MC100EP140	ONSEMI	获取价格	3.3VECL Phase-Frequency Detector
MC100EP140_06	ONSEMI	获取价格	3.3V ECL Phase−Frequency Detector
MC100EP140D	ONSEMI	获取价格	3.3VECL Phase-Frequency Detector
MC100EP140DG	ONSEMI	获取价格	3.3V ECL Phase−Frequency Detector
MC100EP140DR2	ONSEMI	获取价格	3.3VECL Phase-Frequency Detector
MC100EP140DR2G	ONSEMI	获取价格	3.3V ECL Phase−Frequency Detector
MC100EP142FA	ONSEMI	获取价格	3.3 V / 5 V ECL 9-Bit Shift Register
MC100EP142FA	MICROCHIP	获取价格	MC100EP142FA
MC100EP142FAG	ONSEMI	获取价格	3.3 V / 5 V ECL 9-Bit Shift Register
MC100EP142FAR2	ONSEMI	获取价格	3.3 V / 5 V ECL 9-Bit Shift Register

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