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MC100EP14DTG

更新时间： 2024-02-22 16:52:56
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
9页 132K
描述
3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver

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MC100EP14DTG 数据手册

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MC100EP14  
3.3V / 5Vꢀ1:5 Differential  
ECL/PECL/HSTL Clock Driver  
Description  
The MC100EP14 is a low skew 1−to−5 differential driver, designed with  
clock distribution in mind, accepting two clock sources into an input  
multiplexer. The ECL/PECL input signals can be either differential or  
http://onsemi.com  
single−ended (if the V output is used). HSTL inputs can be used when  
BB  
the LVEP14 is operating under PECL conditions.  
The EP14 specifically guarantees low output−to−output skew. Optimal  
design, layout, and processing minimize skew within a device and from  
device to device.  
To ensure that the tight skew specification is realized, both sides of  
any differential output need to be terminated even if only one output is  
being used. If an output pair is unused, both outputs may be left open  
(unterminated) without affecting skew.  
TSSOP−20  
DT SUFFIX  
CASE 948E  
The common enable (EN) is synchronous, outputs are enabled/  
disabled in the LOW state. This avoids a runt clock pulse when the  
device is enabled/disabled as can happen with an asynchronous  
control. The internal flip flop is clocked on the falling edge of the input  
clock, therefore all associated specification limits are referenced to the  
negative edge of the clock input.  
MARKING DIAGRAM*  
20  
100  
EP14  
ALYWG  
G
The MC100EP14, as with most other ECL devices, can be operated  
from a positive V supply in PECL mode. This allows the EP14 to be  
CC  
used for high performance clock distribution in 5.0 V systems.  
Designers can take advantage of the EP14’s performance to distribute  
low skew clocks across the backplane or the board.  
1
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
Features  
• 400 ps Typical Propagation Delay  
• 100 ps Device−to−Device Skew  
• 25 ps Within Device Skew  
W
= Work Week  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
• Maximum Frequency > 2 GHz Typical  
• The 100 Series Contains Temperature Compensation  
• PECL and HSTL Mode:  
*For additional marking information, refer to  
Application Note AND8002/D.  
V
= 3.0 V to 5.5 V with V = 0 V  
CC  
EE  
• NECL Mode:  
= 0 V with V = −3.0 V to −5.5 V  
• Open Input Default State  
• These are Pb−Free Devices  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
V
CC  
EE  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 5  
MC100EP14/D  
1234567...9

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MC100EP14DTG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP139DWR2G ONSEMI

完全替代

 3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation C
MC100EP14DTR2G ONSEMI

完全替代

 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver
SY100EP14UK4GTR MICREL

类似代替

 2.5V/3.3V/5V 1:5 LVPECL/PECL/ECL/HSTL 2GHz CLOCK DRIVER WITH 2:1 DIFFERENTIAL INPUT MUX

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