Datasheet > MC100EP131FA

MC100EP131FA

更新时间： 2024-11-23 22:13:15

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
10页	94K
描述
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

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替代型号

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MC100EP131FA 数据手册

MC10EP131, MC100EP131

3.3V / 5VꢀECL Quad D

Flip−Flop with Set, Reset,

and Differential Clock

The MC10/100EP131 is a Quad Master−slaved D flip−flop with

common set and separate resets. The device is an expansion of the

E131 with differential common clock and individual clock enables.

With AC performance faster than the E131 device, the EP131 is ideal

for applications requiring the fastest AC performance available.

Each flip−flop may be clocked separately by holding Common

http://onsemi.com

MARKING

DIAGRAM*

Clock (C ) LOW and C HIGH, then using the differential Clock

Enable inputs for clocking (C , C ).

0−3 0−3

Common clocking is achieved by holding the differential inputs

MCXXX

EP131

LQFP−32

FA SUFFIX

CASE 873A

LOW and C

HIGH while using the differential Common

0−3

Clock (C ) to clock all four flip−flops. When left floating open, any

AWLYYWW

differential input will disable operation due to input pulldown resistors

forcing an output default state.

Individual asynchronous resets (R ) and an asynchronous set

0−3

(SET) are provided.

Data enters the master when both C and C

transfers to the slave when either C or C (or both) go HIGH.

The 100 Series contains temperature compensation.

XXX = 10 or 100

= Assembly Location

WL = Wafer Lot

YY = Year

are LOW, and

0−3

WW = Work Week

• 460 ps Typical Propagation Delay

• Maximum Frequency > 3 GHz Typical

• Differential Individual and Common Clocks

• Individual Asynchronous Resets

• Asynchronous Set

*For additional information, see Application Note

AND8002/D

ORDERING INFORMATION

†

Device

Package

Shipping

• PECL Mode Operating Range: V = 3.0 V to 5.5 V

MC10EP131FA

LQFP−32

250 Units/Tray

with V = 0 V

MC10EP131FAR2 LQFP−32 2000 Tape & Reel

MC100EP131FA LQFP−32 250 Units/Tray

• NECL Mode Operating Range: V = 0 V

with V = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

MC100EP131FAR2 LQFP−32 2000 Tape & Reel

• Q Output Will Default LOW with Inputs Open or at V

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

January, 2004 − Rev. 7

MC10EP131/D

12 3 4 5 6 7...10

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MC100EP131FA 替代型号

型号	品牌	替代类型	描述	数据表
MC100EP131FAR2	ONSEMI	完全替代	3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
MC100EP451FA	ONSEMI	类似代替	3.3V / 5VECL 6-Bit Differential Register with Master Reset
MC100EP451FAG	ONSEMI	功能相似	3.3V / 5VECL 6-Bit Differential Register with Master Reset

与MC100EP131FA相关器件

型号	品牌	获取价格	描述	数据表
MC100EP131FAG	ROCHESTER	获取价格	100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32, LEAD FREE,
MC100EP131FAG	ONSEMI	获取价格	四路 D 型触发器，带设置、重置和差分时钟
MC100EP131FAR2	ONSEMI	获取价格	3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
MC100EP131FAR2	ROCHESTER	获取价格	100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32, LQFP-32
MC100EP131FAR2G	ONSEMI	获取价格	Quad D Flip-Flop with Set, Reset, and Differential Clock, 32 LEAD LQFP 7x7, 0.8P, 2000-REE
MC100EP131MNG	ROCHESTER	获取价格	100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, QCC32, 5 X 5 MM, 1
MC100EP131MNR4G	ROCHESTER	获取价格	100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, QCC32, 5 X 5 MM, 1
MC100EP131MNR4G	ONSEMI	获取价格	Quad D Flip-Flop with Set, Reset, and Differential Clock, QFN32, 5x5, 0.5P, 3.1x3.1EP, 100
MC100EP139	ONSEMI	获取价格	±2/4, ±4./5/6 Clock Generation Chip
MC100EP139DT	ONSEMI	获取价格	±2/4, ±4./5/6 Clock Generation Chip

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