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MC100EP131FAR2 PDF预览

MC100EP131FAR2

更新时间： 2024-01-02 03:31:53
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路时钟
页数 文件大小 规格书
10页 94K
描述
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

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MC100EP131FAR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP-32
针数：32Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.67
其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列：100E
JESD-30 代码：S-PQFP-G32JESD-609代码：e0
长度：7 mm逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：3000000000 Hz位数：4
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP32,.35SQ,32
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：240
电源：-4.5 V最大电源电流（ICC）：130 mA
传播延迟（tpd）：0.6 ns认证状态：Not Qualified
座面最大高度：1.6 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn80Pb20)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：7 mmBase Number Matches：1

MC100EP131FAR2 数据手册

 浏览型号MC100EP131FAR2的Datasheet PDF文件第2页浏览型号MC100EP131FAR2的Datasheet PDF文件第3页浏览型号MC100EP131FAR2的Datasheet PDF文件第4页浏览型号MC100EP131FAR2的Datasheet PDF文件第5页浏览型号MC100EP131FAR2的Datasheet PDF文件第6页浏览型号MC100EP131FAR2的Datasheet PDF文件第7页 
MC10EP131, MC100EP131  
3.3V / 5VꢀECL Quad D  
Flip−Flop with Set, Reset,  
and Differential Clock  
The MC10/100EP131 is a Quad Master−slaved D flip−flop with  
common set and separate resets. The device is an expansion of the  
E131 with differential common clock and individual clock enables.  
With AC performance faster than the E131 device, the EP131 is ideal  
for applications requiring the fastest AC performance available.  
Each flip−flop may be clocked separately by holding Common  
http://onsemi.com  
MARKING  
DIAGRAM*  
Clock (C ) LOW and C HIGH, then using the differential Clock  
C
C
Enable inputs for clocking (C , C ).  
0−3 0−3  
Common clocking is achieved by holding the differential inputs  
MCXXX  
EP131  
LQFP−32  
FA SUFFIX  
CASE 873A  
C
LOW and C  
HIGH while using the differential Common  
0−3  
0−3  
Clock (C ) to clock all four flip−flops. When left floating open, any  
AWLYYWW  
C
differential input will disable operation due to input pulldown resistors  
forcing an output default state.  
32  
Individual asynchronous resets (R ) and an asynchronous set  
0−3  
1
(SET) are provided.  
Data enters the master when both C and C  
transfers to the slave when either C or C (or both) go HIGH.  
The 100 Series contains temperature compensation.  
XXX = 10 or 100  
= Assembly Location  
WL = Wafer Lot  
YY = Year  
A
are LOW, and  
C
0−3  
C
0−3  
WW = Work Week  
• 460 ps Typical Propagation Delay  
• Maximum Frequency > 3 GHz Typical  
• Differential Individual and Common Clocks  
• Individual Asynchronous Resets  
• Asynchronous Set  
*For additional information, see Application Note  
AND8002/D  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
MC10EP131FA  
LQFP−32  
250 Units/Tray  
with V = 0 V  
EE  
MC10EP131FAR2 LQFP−32 2000 Tape & Reel  
MC100EP131FA LQFP−32 250 Units/Tray  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
• Open Input Default State  
• Safety Clamp on Inputs  
MC100EP131FAR2 LQFP−32 2000 Tape & Reel  
• Q Output Will Default LOW with Inputs Open or at V  
EE  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
January, 2004 − Rev. 7  
MC10EP131/D  
1234567...10

中文翻译

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MC100EP131FAR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP451FAR2G ONSEMI

完全替代

 3.3V / 5V ECL 6−Bit Differential Register with Master Reset
MC100EP131FA ONSEMI

完全替代

 3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock
MC100EP451FAG ONSEMI

类似代替

 3.3V / 5VECL 6-Bit Differential Register with Master Reset

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