5秒后页面跳转
捷配首页

Datasheet > MC100EP111FAR2
MC100EP111FAR2 PDF预览

MC100EP111FAR2

更新时间： 2024-11-27 14:53:11
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
5页 284K
描述
100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32

阅读下载

中文翻译

获取价格

MC100EP111FAR2 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：32
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.37其他特性：ECL MODE: VCC = 0V WITH VEE = -2.25V TO -3.8V
系列：100E输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQFP-G32长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：32
实输出次数：10封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE传播延迟（tpd）：0.65 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.065 ns
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.8 V
最小供电电压 (Vsup)：2.25 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：ECL
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD宽度：7 mm
Base Number Matches：1

MC100EP111FAR2 数据手册

 浏览型号MC100EP111FAR2的Datasheet PDF文件第2页浏览型号MC100EP111FAR2的Datasheet PDF文件第3页浏览型号MC100EP111FAR2的Datasheet PDF文件第4页浏览型号MC100EP111FAR2的Datasheet PDF文件第5页 
Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
ꢀ
ꢁ
ꢂ
ꢁ
ꢃ
ꢁ
ꢄ
ꢅ
Order this document  
by MC100EP111/D  
ꢄ
ꢗ
ꢆ
ꢘ
ꢇ
ꢄ
ꢈ
ꢉ
ꢗ
ꢆ
ꢘ
ꢊ
ꢋ
ꢄ
ꢌ
ꢍ
ꢎ
ꢜ
ꢏ
ꢐ
ꢏ
ꢑ
ꢒꢓꢔꢔꢎ ꢕꢎꢖ ꢋ ꢓꢌ ꢊ  
ꢊꢆꢝ ꢞ ꢒꢕ ꢓ ꢟꢎꢕ  
ꢀ
ꢘ
ꢏ
ꢑ
ꢑ
ꢗ
ꢚ
ꢏ
ꢏ
ꢏ
ꢙ
ꢚ
ꢙ
ꢛ
ꢂ
ꢄ
ꢘ
See Upgrade Product – MC100ES6111  
The MC100EP111 is a low skew 1–to–10 differential driver, designed  
with clock distribution in mind. It accepts two clock sources into an input  
multiplexer. The ECL/PECL input signals can be either differential or  
single–ended if the VBB output is used. HSTL inputs can be used when  
the EP111 is operating under PECL conditions. The selected signal is  
fanned out to 10 identical differential outputs.  
LOW–VOLTAGE  
1:10 DIFFERENTIAL  
ECL/PECL/HSTL  
CLOCK DRIVER  
• 100ps Part–to–Part Skew typical  
• 35ps Output–to–Output Skew typical  
• Differential Design  
• VBB Output  
• Low Voltage VEE Range of –2.25 to –3.8V for ECL  
• Low Voltage VCC Range of +2.25 to +3.8V for PECL and HSTL  
• 75kΩ Input Pulldown Resistors  
• ECL/PECL Outputs  
FA SUFFIX  
32–LEAD LQFP PACKAGE  
CASE 873A  
The EP111 is specifically designed, modeled and produced with low  
skew as the key goal. Optimal design and layout serve to minimize  
gate–to–gate skew within a device, and empirical modeling is used to  
determine process control limits that ensure consistent tpd distributions  
from lot to lot. The net result is a dependable, guaranteed low skew  
device.  
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into  
50Ω, even if only one side is being used. In most applications, all ten differential pairs will be used and therefore terminated. In  
the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as  
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of  
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will  
mean a loss of skew margin.  
7
The MC100EP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows  
the EP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the  
EP111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or  
Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL,  
designers should refer to Motorola Application Note AN1406/D.  
The MC100EP111 may be driven single–endedly utilizing the VBB bias output with the  
input. If a single–ended signal  
CLK0  
input and bypassed to ground via a 0.01 µF capacitor. The VBB  
is to be used, the VBB pin should be connected to the  
CLK0  
output can only source/sink 0.2mA; therefore, it should be used as a switching reference for the MC100EP111 only. Part–to–Part  
Skew specifications are not guaranteed when driving the MC100EP111 single–endedly.  
Rev 1  
624  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
For More Information On This Product,  
Go to: www.freescale.com  
12345

中文翻译

下载PDF

与MC100EP111FAR2相关器件

型号 品牌 获取价格 描述 数据表
MC100EP116 ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116FA ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116FAG ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116FAR2 ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116FAR2G ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116MNG ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116MNR4G ONSEMI

获取价格

 		3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP11D ONSEMI

获取价格

 		3.3V / 5VECL 1:2 Differential Fanout Buffer
MC100EP11DG ONSEMI

获取价格

 		3.3V / 5V ECL 1:2 Differential Fanout Buffer
MC100EP11DGH ONSEMI

获取价格

 		Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V, SOIC-8 Narrow Body, 98-T

与MC100EP111FAR2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证