Datasheet > 驱动程序和接口 > 线路驱动器或接收器> MC100EP116MNG

MC100EP116MNG

更新时间： 2024-11-24 05:22:27

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器接口集成电路
页数	文件大小	规格书
11页	173K
描述
3.3 V / 5 V Hex Differential Line Receiver/Driver

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中文翻译

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MC100EP116MNG 数据手册

MC10EP116, MC100EP116

3.3 V / 5 VꢀHex Differential

Line Receiver/Driver

Description

The MC10EP116/100EP116 is a 6-bit differential line receiver

based on the EP16 device. The 3.0 GHz bandwidth provided by the

high frequency outputs makes the device ideal for buffering of very

high speed oscillators.

http://onsemi.com

MARKING

The V pin, an internally generated voltage supply, is available to

DIAGRAM*

this device only. For single−ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

MCxxx

EP116

AWLYYWWG

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

The design incorporates two stages of gain, internal to the device,

making it an excellent choice for use in high bandwidth amplifier

applications.

LQFP−32

FA SUFFIX

CASE 873A

The differential inputs have internal clamp structures which will

force the Q output of a gate in an open input condition to go to a LOW

state. Thus, inputs of unused gates can be left open and will not affect

the operation of the rest of the device. Note that the input clamp will

MCxxx

EP116

take affect only if both inputs fall 2.5 V below V

AWLYYWWG

QFN32

MN SUFFIX

CASE 488AM

The 100 Series contains temperature compensation.

Features

• 260 ps Typical Propagation Delay

• Maximum Frequency > 3 GHz Typical

xxx

= 10 or 100

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

• PECL Mode Operating Range: V = 3.0 V to 5.5 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

G or G = Pb−Free Package

with V = −3.0 V to −5.5 V

(Note: Microdot may be in either location)

• Open Input Default State

• Safety Clamp on Inputs

*For additional marking information, refer to

Application Note AND8002/D.

• Q Output Will Default LOW with Inputs Open or at V

• V Output

• Pb−Free Packages are Available

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

Publication Order Number:

December, 2006 − Rev. 11

MC10EP116/D

12 3 4 5 6 7...11

中文翻译

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与MC100EP116MNG相关器件

型号	品牌	获取价格	描述	数据表
MC100EP116MNR4G	ONSEMI	获取价格	3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP11D	ONSEMI	获取价格	3.3V / 5VECL 1:2 Differential Fanout Buffer
MC100EP11DG	ONSEMI	获取价格	3.3V / 5V ECL 1:2 Differential Fanout Buffer
MC100EP11DGH	ONSEMI	获取价格	Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V, SOIC-8 Narrow Body, 98-T
MC100EP11DR2	ONSEMI	获取价格	3.3V / 5VECL 1:2 Differential Fanout Buffer
MC100EP11DR2G	ONSEMI	获取价格	3.3V / 5V ECL 1:2 Differential Fanout Buffer
MC100EP11DR2GH	ONSEMI	获取价格	Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V, SOIC-8 Narrow Body, 2500
MC100EP11DT	ONSEMI	获取价格	3.3V / 5VECL 1:2 Differential Fanout Buffer
MC100EP11DTG	ONSEMI	获取价格	3.3V / 5V ECL 1:2 Differential Fanout Buffer
MC100EP11DTR2	ONSEMI	获取价格	3.3V / 5VECL 1:2 Differential Fanout Buffer

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