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MC100EP11DGH PDF预览

MC100EP11DGH

更新时间: 2024-10-01 21:11:27
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 161K
描述
Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V, SOIC-8 Narrow Body, 98-TUBE

MC100EP11DGH 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.67其他特性:NECL MODE: VCC=0 WITH VEE = -3.0V TO -5.5V
系列:10EP输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:8实输出次数:2
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:-3.0/-5.5 VProp。Delay @ Nom-Sup:0.3 ns
传播延迟(tpd):0.3 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.12 ns座面最大高度:1.75 mm
子类别:Clock Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

MC100EP11DGH 数据手册

 浏览型号MC100EP11DGH的Datasheet PDF文件第2页浏览型号MC100EP11DGH的Datasheet PDF文件第3页浏览型号MC100EP11DGH的Datasheet PDF文件第4页浏览型号MC100EP11DGH的Datasheet PDF文件第5页浏览型号MC100EP11DGH的Datasheet PDF文件第6页浏览型号MC100EP11DGH的Datasheet PDF文件第7页 
MC10EP11, MC100EP11  
3.3V / 5VꢀECL 1:2  
Differential Fanout Buffer  
Description  
The MC10/100EP11 is a differential 1:2 fanout buffer. The device is  
pin and functionally equivalent to the LVEL11 device. With AC  
performance much faster than the LVEL11 device, the EP11 is ideal  
for applications requiring the fastest AC performance available.  
The 100 Series contains temperature compensation.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
8
Features  
8
HEP11  
ALYW  
G
KEP11  
ALYW  
G
220 ps Typical Propagation Delay  
Maximum Clock Frequency > 3 GHz Typical  
1
SOIC8  
D SUFFIX  
CASE 751  
1
1
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 3.0 V to 5.5 V  
EE  
8
8
1
8
Open Input Default State  
Safety Clamp on Inputs  
Q Outputs Will Default LOW with Inputs Open or at V  
PbFree Packages are Available  
1
HP11  
KP11  
ALYWG  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
G
G
EE  
1
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
H
K
= MC10  
= MC100  
A
L
= Assembly Location  
= Wafer Lot  
5K = MC10  
2Z = MC100  
Y
W
G
= Year  
= Work Week  
= PbFree Package  
M
= Date Code  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
October, 2009 Rev. 10  
MC10EP11/D  

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