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MC100EP116FA PDF预览

MC100EP116FA

更新时间: 2024-11-27 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
11页 173K
描述
3.3 V / 5 V Hex Differential Line Receiver/Driver

MC100EP116FA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.29Is Samacsys:N
其他特性:CAN ALSO OPERATE WITH -3V TO -5.5V SUPPLY IN NECL MODE差分输出:YES
驱动器位数:6输入特性:DIFFERENTIAL
接口集成电路类型:LINE TRANSCEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm标称负供电电压:-4.5 V
功能数量:6端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:-4.5 V认证状态:Not Qualified
最大接收延迟:0.34 ns接收器位数:6
座面最大高度:1.6 mm子类别:Line Driver or Receivers
最大压摆率:95 mA最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
最大传输延迟:0.34 ns宽度:7 mm
Base Number Matches:1

MC100EP116FA 数据手册

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MC10EP116, MC100EP116  
3.3 V / 5 VꢀHex Differential  
Line Receiver/Driver  
Description  
The MC10EP116/100EP116 is a 6-bit differential line receiver  
based on the EP16 device. The 3.0 GHz bandwidth provided by the  
high frequency outputs makes the device ideal for buffering of very  
high speed oscillators.  
http://onsemi.com  
MARKING  
The V pin, an internally generated voltage supply, is available to  
DIAGRAM*  
BB  
this device only. For singleended input conditions, the unused  
differential input is connected to V as a switching reference voltage.  
BB  
V
may also rebias AC coupled inputs. When used, decouple V  
CC  
BB  
BB  
MCxxx  
EP116  
AWLYYWWG  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
to 0.5 mA. When not used, V should be left open.  
The design incorporates two stages of gain, internal to the device,  
making it an excellent choice for use in high bandwidth amplifier  
applications.  
BB  
LQFP32  
FA SUFFIX  
CASE 873A  
The differential inputs have internal clamp structures which will  
force the Q output of a gate in an open input condition to go to a LOW  
state. Thus, inputs of unused gates can be left open and will not affect  
the operation of the rest of the device. Note that the input clamp will  
1
MCxxx  
EP116  
32  
1
take affect only if both inputs fall 2.5 V below V  
.
CC  
AWLYYWWG  
QFN32  
MN SUFFIX  
CASE 488AM  
The 100 Series contains temperature compensation.  
G
Features  
260 ps Typical Propagation Delay  
Maximum Frequency > 3 GHz Typical  
xxx  
A
= 10 or 100  
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
G or G = PbFree Package  
with V = 3.0 V to 5.5 V  
EE  
(Note: Microdot may be in either location)  
Open Input Default State  
Safety Clamp on Inputs  
*For additional marking information, refer to  
Application Note AND8002/D.  
Q Output Will Default LOW with Inputs Open or at V  
EE  
V Output  
PbFree Packages are Available  
BB  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 11  
MC10EP116/D  

MC100EP116FA 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP116FAR2 ONSEMI

完全替代

3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116FAG ONSEMI

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3.3 V / 5 V Hex Differential Line Receiver/Driver
MC100EP116FAR2G ONSEMI

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3.3 V / 5 V Hex Differential Line Receiver/Driver

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