Datasheet > MC100E175

MC100E175

更新时间： 2024-11-22 22:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		锁存器
页数	文件大小	规格书
4页	110K
描述
9-BIT LATCH WITH PARITY

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数据手册

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MC100E175 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E175 is a 9-bit latch. It also features a tenth latched

output, ODDPAR, which is formed as the odd parity of the nine data

inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).

The E175 can also be used to generate byte parity by using D8 as the

parity-type select (L = even parity, H = odd parity), and using ODDPAR as

the byte parity output.

The LEN pin latches the data when asserted with a logical high and

makes the latch transparent when placed at a logic low level.

9-BIT LATCH

WITH PARITY

• 9-Bit Latch

• Parity Detection/Generation

• 800ps Max. D to Output

• Reset

• Extended 100E V

Range of – 4.2V to – 5.46V

• Internal 75kΩ Input Pulldown Resistors

Pinout: 28-Lead PLCC (Top View)

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

CCO

LOGIC DIAGRAM

LEN

CCO

BITS

1–7

CCO

* All V

and V

pins are tied together on the die.

CCO

PIN NAMES

ODDPAR

Function

– D

LEN

– Q

ODDPAR

Data Inputs

Latch Enable

Master Reset

Data Outputs

Parity Output

LEN

12/93

Motorola, Inc. 1996

REV 2

2–1

12 3 4

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