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MC100E175FNR2 PDF预览

MC100E175FNR2

更新时间: 2024-11-23 05:10:27
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
8页 81K
描述
5V ECL 9-Bit Latch With Parity

MC100E175FNR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-28
针数:28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.8
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.5V
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
逻辑集成电路类型:D LATCH湿度敏感等级:1
位数:9功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-4.5 V最大电源电流(ICC):152 mA
Prop。Delay @ Nom-Sup:1.45 ns传播延迟(tpd):0.8 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:LOW LEVEL宽度:11.505 mm
最小 fmax:700 MHzBase Number Matches:1

MC100E175FNR2 数据手册

 浏览型号MC100E175FNR2的Datasheet PDF文件第2页浏览型号MC100E175FNR2的Datasheet PDF文件第3页浏览型号MC100E175FNR2的Datasheet PDF文件第4页浏览型号MC100E175FNR2的Datasheet PDF文件第5页浏览型号MC100E175FNR2的Datasheet PDF文件第6页浏览型号MC100E175FNR2的Datasheet PDF文件第7页 
MC10E175, MC100E175  
5VꢀECL 9-Bit Latch With  
Parity  
Description  
The MC10E/100E175 is a 9-bit latch. It also features a tenth latched  
output, ODDPAR, which is formed as the odd parity of the nine data  
inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).  
The E175 can also be used to generate byte parity by using D8 as the  
parity-type select (L = even parity, H = odd parity), and using  
ODDPAR as the byte parity output.  
http://onsemi.com  
The LEN pin latches the data when asserted with a logical high and  
makes the latch transparent when placed at a logic low level.  
Features  
PLCC−28  
FN SUFFIX  
CASE 776  
9-Bit Latch  
Parity Detection/Generation  
800 ps Max. D to Output  
Reset  
PECL Mode Operating Range: V = 4.2 V to 5.5 V  
CC  
with V = 0 V  
MARKING DIAGRAM*  
EE  
NECL Mode Operating Range: V = 0 V  
1
CC  
with V = −4.2 V to −5.5 V  
EE  
Internal Input 50 kW Pulldown Resistors  
MCxxxE175FNG  
AWLYYWW  
ESD Protection: Human Body Model; > 2 kV,  
Machine Model; > 200 V  
Charged Device MOdel; > 2 kV  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
Moisture Sensitivity Level:  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
Pb = 1  
Pb−Free = 3  
For Additional Information, see Application Note AND8003/D  
Flammability Rating: UL 94 V−0 @ 0.125 in,  
Oxygen Index: 28 to 34  
Transistor Count = 416 devices  
Pb−Free Packages are Available*  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 9  
MC10E175/D  

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